RTL Design Engineer

RTL Design & Development: Write and debug synthesizable RTL code using Verilog or SystemVerilog for application-specific integrated circuits (ASICs). Static Verification: Execute front-end quality checks, including RTL Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC). Synthesis & Optimization: Run logic synthesis to generate optimized gate-level netlists targeting strict constraints for power, area, and timing. Cross-functional Collaboration: Work closely with architecture, physical design, and firmware teams to translate high-level specifications into physical silicon. Automation: Develop scripting tools (e.g., Python, Perl, Tcl) to automate implementation and testing flows. Minimum Qualifications: Education: B.S. or M.S. degree in Computer Science, Electrical Engineering, or a closely related technical field. Technical Skills: Strong proficiency in SystemVerilog, HDL coding, and knowledge of front-end ASIC design flows. Verification Experience: Hands-on experience with linting, formal verification, and SoC integration (Reset, PLLs, Clocking). Communication: Ability to collaborate with multi-functional teams and handle hardware-software interface discussions #J-18808-Ljbffr