Senior Design Verification Engineer
Canvendor
Senior Design Verification Engineer
Location: San Jose CA
Experience Level: 10+ years
Job Description
Job Summary
We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.
Key responsibilities
• End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
• Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.
• Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.
• Drive coverage closure and sign-off by defining metrics, analyzing gaps, and
• ensuring comprehensive verification across corner cases and stress scenarios
Vacancy posted 15 hours ago
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