Senior Rtl Design Engineer (Asic) - Ai Accelerators

Mentium Technologies Inc. is seeking an experienced ASIC RTL Design Engineer to design, implement and test complex digital RTL components to be used in Mentium’s digital AI accelerator and get involved with the integration of the PCIe IP to the SOC. In this role, you will collaborate closely with system architects, verification teams, physical design, and software teams to deliver high-quality designs that meet stringent performance, power, and area (PPA) goals. This is an excellent opportunity for an individual with strong skills and deep expertise in RTL design, verification, and front-end EDA tools.

This role offers an exciting opportunity to learn and work with cutting-edge vision AI accelerators, machine and deep learning algorithms, and make a meaningful impact on the development of a co-designed robust, client-facing hardware-software library.

Responsibilities

• Manage and develop RTL components for complex systems and AI accelerators.
• Define detailed micro-architectures based on high-level product specifications and requirements.
• Write clean, efficient, synthesizable and reusable Verilog/SystemVerilog code with a focus on meeting frequency, power, and area targets.
• Help with Integrating complex IPs (e.G., PCIe) into SoCs and perform relevant front-end integration activities (lint, CDC checks, synthesis, ECO).
• Work with verification teams to develop meaningful SystemVerilog assertions, constraints, checkers, and test benches.
• Debug RTL code using modern simulation tools and waveform viewers, ensuring coverage closure and functional correctness.
• Collaborate on timing closure with physical design teams, optimizing for performance, power, and area.
• Coordinate with system architects to align design specifications and functional requirements.
• Collaborate with physical design teams on synthesis, static timing, DFT, and ECO processes.
• Perform power, performance, and area (PPA) trade-offs and drive architectural decisions to meet aggressive project goals.

Required Qualifications

• Master’s or PhD’s in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of RTL design experience with 2+ years of experience in the industry.
• Strong background in digital design principles, finite state machines (FSMs), and clock domain crossing (CDC).
• Proficiency in SystemVerilog.
• Experience with front-end EDA tools (e.G., Synopsys, Cadence) including simulators, linters, and CDC checkers.
• Knowledge of synthesis, static timing analysis, DFT, and ECO flows.
• Skilled in scripting (Perl, Python) for automation and productivity enhancements.
• Proven ability to troubleshoot and optimize designs using simulation tools and waveform viewers.
• Basic knowledge of memory compilers, deep learning algorithms and neural networks

Good to have:

• Prior RTL design experience with microprocessors, SoCs, memory structures and managements, and/or interconnect IP.
• Knowledge of SoC bus interconnect protocols (AXI4, AXI streaming, AHB).
• Experience with compute subsystem memory micro-architecture.
• Validated knowledge of SystemVerilog assertions and verification IP.
• Experience with PCIe interface integration and simulation.
• Experience with designing of systems to accelerate deep neural networks

Why Join Mentium?

At Mentium, you'll be at the forefront of vision AI technology, working alongside a talented team dedicated to innovation. We offer a collaborative environment where your contributions directly influence the development of cutting-edge solutions. Join us to make a meaningful impact in the field of vision AI.

Benefits:

• Competitive compensation packages
• Opportunity to work on diverse, cutting-edge AI projects across a range of industries.
• 401(k)
• Flexible PTO
• Full PPO medical, dental, and vision insurance coverage