Lead CPU Cache Subsystem Design Engineer - Senior Staff
Google LLC
Google is seeking a Senior Staff CPU Cache Subsystem Design Engineer to lead front-end design teams, define microarchitecture, and deliver RTL for next-generation CPU subsystems across target SOCs. You will collaborate with architecture, software, verification, power, DFT, and physical design teams to optimize performance, power, and area. Ideal candidates have a Master's in EE/CS, 15 years in high-performance CPU design, and experience guiding technical teams, with familiarity in Lint, CDC/RDC
#J-18808-LjbffrVacancy posted 3 days ago
Similar jobs that could be interesting for youBased on the Lead CPU Cache Subsystem Design Engineer - Senior Staff in Mountain View, CA vacancy
$240k - $333k
...Senior Staff CPU Cache Subsystem Design Engineer Share Senior Staff CPU Cache Subsystem Design Engineer corporate_fare Google place Austin, TX, USA... ...microarchitecture definition and PPA optimizations. ~ Experience leading technical teams for modern processor subsystems with...SeniorWorldwideGoogle LLC
Mountain View, CA3 days ago- Responsibilities: • Architect, design and implement new features,... ...ISA extensions in RISC-V CPU core generators. •... ...execution units; load-store unit; cache and memory subsystems. • Knowledge of RISC-V architecture... ...others and a belief that engineering is a team sport. •...Senior
Baidu
Sunnyvale, CA3 days ago $136k - $218.5k
...lasting impact on the world. NVIDIA is looking for an Senior ASIC Design Engineer to join our Memory Subsystem Team!Whatyou'llbedoing:As a member of our Memory... ...bridges, hardware-managed coherency and system level caches is a plusExperience with multiple clock domains and...SeniorFull timeNvidia
Santa Clara, CA3 days ago$136k - $218.5k
As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip interconnect network... ...caches.What we need to see:Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or...SeniorFull timeNvidia
Santa Clara, CA4 days ago$136k - $218.5k
We are now looking for a Senior Logic Design Engineer!As a member of our CPU Logic Design Team, you will be responsible for the design of CPU on-chip and off... ...network, MP coherency and last-level and system caches, focusing on such tasks as micro-architectural definition...SeniorFull timeNvidia
Santa Clara, CA5 days ago$168k - $264.5k
We are looking for a Senior CPU Design Engineer! NVIDIA is seeking best-in-class CPU Design Engineers to design the world’s leading CPUs. This position offers you the opportunity to have... ..., high speed designs, ideally in CPU subsystems. Exposure to Computer Architecture...SeniorFull timeRemote workNvidia
Santa Clara, CA2 days ago- ...TypeContract Experience: 5-12+ Years Responsibilities Verify CPU subsystem and standard interfaces using SystemVerilog/UVM. Develop... ...management, and exception handling. Execute regressions, debug RTL/design issues, and drive functional and code coverage closure....Senior
ACL Digital
San Jose, CA3 days ago - ...Google in Mountain View is seeking a seasoned hardware design leader to own end-to-end physical design for top-level CPU blocks. You will drive PPA optimization, pioneering design methodologies and AI/ML-enhanced flows, while addressing complex timing, power, and verification...Senior
Google
Mountain View, CA4 days ago $209.3k - $313.9k
...Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group CPU Engineering General Summary:... ...engineers in the world to create designs that push the envelope on performance... ...our custom CPUs have industry-leading power, performance and area. Roles...SeniorWork experience placementWork from homeWorldwide$69k - $202k
...GlobalFoundries: GlobalFoundries is a leading full-service semiconductor... ...a unique combination of design, development, and... ...eager to become a world-class CPU IP Design Engineer. Responsible for developing... ...Prefetch* Vector data path* Cache and memory subsystemsKnowledge...SeniorFull timeLocal areaGlobalfoundries
Santa Clara, CA1 day ago$192k - $278k
Lead end-to-end physical design strategy and execution for top-level and critical CPU blocks across advanced process nodes.Pioneer novel Physical Design methodologies,... ...iteration loops.Drive technical roadmaps, mentor senior engineering peers, and influence architectural trade-...Google
Mountain View, CA5 days ago- Job Description:Design cost effective controller with... ...multi-nation teams in leading-edge process node and... ...in: - Perform CPU development and design... ...integration for MIPS CPU subsystem. - Explore latest technologies... ...Degree in Electrical Engineering, Computer Science or...Work experience placement
Baidu
Sunnyvale, CA3 days ago - ...Synopsys, Inc. seeks an experienced ASIC physical design engineer to drive timing closure for advanced-node designs and lead signoff readiness across block, subsystem, and full-chip implementations. You will build repeatable design flows using TCL, Python, and Perl...Senior
- ...We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling... ...products. We deliver industry-leading silicon design, IP, simulation and analysis solutions... ...your impact across a team working on subsystems that will ship in products used by millions...Senior
- ...shaping the future. Whether you’re designing next-gen processors, enabling... ...breakthroughs, or bringing leading edge products to market,... ...customer success on the memory subsystem across our silicon portfolio,... ...collaborating with engineers located in different sites and...SeniorNight shift
AMD
San Jose, CA3 days ago - Job Description: Design cost effective controller with... ...multi-nation teams in leading-edge process node and be... ...involved in: - Perform CPU development and design integration for CPU subsystem. - Micro-architecture... ...Master Degree in Electrical Engineering, Computer Science or...Work experience placement
Baidu
Sunnyvale, CA3 days ago $180.2k - $297.2k
.... Come build with us!Role and ResponsibilitiesAs a Senior Staff GPU Design Verification Engineer - Subsystems, you will help shape the verification of one or more... ...a Ph.D.8+ years of hands-on experience in GPU, CPU, or advanced semiconductor design verification.Strong...SeniorHourly payFull timeRelocationSamsung Semiconductor
San Jose, CA5 days ago- ...NVIDIA Corporation in Santa Clara, CA is seeking a Senior ASIC Design Engineer for the Memory Subsystem Team to design high‑performance memory interfaces and interconnects that power world‑class GPUs and SoCs. You will collaborate with architects, verification, physical...Senior
- ...NVIDIA is seeking a Senior ASIC Design Engineer to join our Memory Subsystem Team in Santa Clara. You will collaborate with architects, verification, formal verification and physical design to deliver a world-class memory subsystem solution. You will own micro-architecture...Senior
NVIDIA
Santa Clara, CA4 days ago $163k - $236k
Work with designers, architects, and other stakeholders... ...design blocks at subsystem level by understanding... ...architecture and design engineers to identify important... ...Experienced in ARM or CPU based subsystem verification... ...objectives.Experience leading design verification of...SeniorWorldwideGoogle
Mountain View, CA3 days ago$179k - $256k
Sr. Staff Memory Design EngineerCategoryChip DesignLocationSan Jose, CAExperienceMore than... ...is looking for a high-performance senior memory design engineer to define and design custom memory... ...teams to design TCAM, SRAM, CPU caches with different PPA requirements for...SeniorTemporary workWorldwideMediaTek
San Jose, CA1 day ago$135.9k - $201.13k
...trends, Marvell is a place to thrive, learn, and lead. Your Team, Your ImpactAs a Senior Staff Digital ASIC Design Engineer at Marvell, you will join the DCE -... ...micro‑architecture specifications for complex subsystems, high‑speed datapaths, DSP pipelines, and IP blocks...SeniorPermanent employmentFull timeInternshipWork from homeMarvell
Santa Clara, CA2 days ago$150k - $220k
...) space system that will fundamentally change the design, economics, manufacturing and service delivery associated... ...our overall quality of life. We are seeking a Senior ASIC Design Engineer to join our processor subsystem team, focused on the configuration, integration,...SeniorFull timeWork at officeImmediate startVisa sponsorshipNight shiftE-Space
Saratoga, CA15 days ago$100k
Tenstorrent is leading the industry on cutting-edge... ...performance RISC-V CPU from scratch, and share... ...contributors of all seniorities.We are looking for a talented engineer to join our CPU design team and lead the front... ...RISC‑V CPU and CPU subsystem Work closely with microarchitects...SeniorPermanent employmentTenstorrent
Santa Clara, CA5 days ago$192.1k - $249.6k
.... is a pioneer and a leading company in the global... ...experience excellence. NIO designs, develops,... ...performance bottlenecks across CPU, memory hierarchy, cache, interconnect, and interrupt subsystems. Leverage hardware... ...Science, Electrical Engineering, or a related field....SeniorFull timeTemporary workFlexible hoursNIO USA, INC
San Jose, CA4 days ago- ...Santa Clara seeks a Technical Program Manager to own the Oryon CPU Engineering program, driving development and delivery of CPU IP into... ...experience, and the ability to craft data-driven schedules while reporting progress to senior leadership. #J-18808-Ljbffr Jobleads-USSenior
$280k
RTL IC Design Engineer (Senior, Staff or Principal)Compensation:For Senior - up to approx $280k total comp ($120-160k base, 20% bonus + RSUs)For... ...RSUs)Shape the Future of AI InfrastructureJoin an industry-leading engineering team developing the high-performance silicon...SeniorCyberCoders
San Jose, CA16 hours ago$250k - $300k
...This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster... ...inference.Key ResponsibilitiesWork with architects, designers, post silicon and software engineers to ensure a high-quality design that works first silicon...SeniorCerebras Systems
Sunnyvale, CA2 days ago$150k - $250k
Job Title: Senior ASIC Design EngineerJob Location: Santa Clara, CA or Boston... .../O, AI Accelerator, Memory Subsystem DesignPosition OverviewWe... ...skilled Senior ASIC Design Engineer to lead the design and development... ...of memory subsystems and cache coherence mechanisms.Mentor...SeniorCyberCoders
Santa Clara, CA5 days ago- Role OverviewWe are seeking a Senior Staff Storage Backend Engineer to design and optimize the next generation... ...optimize storage performance across CPU, memory, caching, scheduling, and data movement... ..., or high-performance I/O subsystems.Deep understanding of storage architecture...Senior
DataDirect Networks
Santa Clara, CA2 days ago
Do you want to receive more vacancies?
Subscribe and receive similar vacancies to Lead CPU Cache Subsystem Design Engineer - Senior Staff. Be the first to apply!
Related searches
- product engineer Mountain View, CA
- senior manager product engineering Mountain View, CA
- new product engineer Mountain View, CA
- senior fpga design engineer Mountain View, CA
- senior software design engineer Mountain View, CA
- sr. product engineer Mountain View, CA
- digital design engineer Mountain View, CA
- manufacturing design engineer Mountain View, CA
- rtl design engineer Mountain View, CA
- soc design engineer Mountain View, CA