SoC Design Verification Engineer | UVM & Power Debug
$80k - $160kAvanciers Inc.
A technology consulting firm is seeking a Design Verification Engineer to join the team for a full-time project. The role involves understanding SV and UVM, building verification environments, and collaborating with various technical teams. Candidates should have solid debugging skills and the ability to develop test plans. Compensation ranges from $80,000 to $160,000, depending on experience and skills. #J-18808-Ljbffr Avanciers Inc.
Vacancy posted 1 day ago
Similar jobs that could be interesting for youBased on the SoC Design Verification Engineer | UVM & Power Debug in Austin, TX vacancy
- ...SoC Design Verification, SystemVerilog, UVM, Object-Oriented Programming, Python, C++, Java,... ...Interaction, Multi-chip Debug, Coverage-driven Verification... ...thatApple’s Silicon Engineering Group has embarked upon to... ...standardmethodologies on low-power architecture, outstanding...SuggestedFlexible hours
Y Axis Inc
Austin, TX10 hours ago $147.4k - $272.1k
...Apple’s Silicon Engineering Group has... ...sophisticated SOCs that are driving... ...highly reusable UVM TB, implement effective... ...on low-power architecture, outstanding... ...methodology, verification on accelerated... ...multi-chip SOC debug architecture.... ...As a Design Verification Engineer...SuggestedRelocationFlexible hoursApple
Austin, TX3 days ago- Overview Join to apply for the SoC Design Verification Engineer role at Inspire Semiconductor, Inc. Get AI-powered advice on this job and more... ...designs. Create and maintain UVM/SystemVerilog based testbenches and environments. Write, debug, and execute constrained-...SuggestedFull time
- Apple’s Silicon Engineering Group seeks a Design Verification Engineer in Austin, TX to verify complex Cellular SoCs for 5G platforms. You will craft reusable UVM testbenches, implement coverage-driven strategies... ..., addressing multi-chip debug and tape-out #J-18808-Ljbffr...Suggested
- ...looking for candidates for a design verification role in Austin, Texas.... ...Responsibilities include defining IP/SoC verification plans,... ...or M.S degree in Electrical Engineering, Computer Engineering, or Computer... ...Verilog, SystemVerilog, and UVM methodology. This position...Suggested
- ...advanced electronics the power to report on their... ...End (DV focused) Engineer to join a global... ...: SystemVerilog / UVM Advanced Testbench... ...Experience debugging RTL, gate-level, and... ...foundation in digital design, SoC architecture, and... ...CDC/RDC, formal verification, and low-power flows...Work at office
proteanTecs
Austin, TX10 hours ago $200k - $320k
...re looking for a experienced Design Verification engineer with at least 5 years of pre... ...IP, subsystems, and/or SoC system level verification from... ...protocol verification ~ Debug for functional closure of complex... ...~ Well-versed in UVM methodology and testbench architecture...H1bVisa sponsorshipWork visaFlexible hoursNight shiftDensityAI
Austin, TXa month ago- ...position involves design verification of next generation IP’s /SoC’s with emphasis on... ...off performance and power along with... ...Experience in SV and UVM testbench development... ...Electrical and/or Computer Engineering Minimum... ...Excellent simulation debugging skills, with the...Full time
- ...propelled by the top engineers in mixed-signal processing... ...and innovative Design Verification Engineer to join a world... ...verification domains including UVM-based testbench... ...regression triage, and debug, resolving functional... ...signal ASICs in complex SoC environments....
$126.1k - $170.5k
Graduate Design Verification Engineer Join to apply for the Graduate Design... ...are high-performance, power efficient and reliable... ...-performance server SoC. The collection of silicon... ..., system controllers, debug and trace and IP... ...Out Experience with UVM and/or formal verification...Full timeWork at officeLocal area- ...adaptive, self‑motivated design verification engineer to join our growing... ...in System Verilog and UVM to complete verification... ...leading formal tools Debug tests with design... ...block level/full chip SOCs and FPGAs. Strong understanding... ...level simulation, power verification, reset...Night shift
- Get AI-powered advice on this job and more exclusive features... ...seeking a highly skilled Design Verification Engineer to join our team for an... ...understanding of SV and UVM and good debugging skills. Understanding of... ...environments for IP/subsystem/SoC level testing Develop...Full time
- ...massive scale inference. Powered by the next... ...Senior, Staff level Design Verification Engineer for Pre-Silicon Verification... ...block and top-level SoC for next-generation Dojo... ...highly reusable UVM testbenches, writing... ...planning, TB-development, debug and coverage closure...Hourly payTemporary workFlexible hoursNight shift
$108k - $184k
Join to apply for the ASIC Design Verification Engineer - New College Grad 2026 role... ...The NVIDIA System‑On‑Chip (SOC) group is looking for an entry... ...verify the design. Create the UVM components, sequences, tests... ...simulation tools, and debug tools like Verdi. With industry...Full time$163k - $237k
...degree in Electrical Engineering, Computer Engineering... ...of experience in both Design Verification (UVM/SystemVerilog) and... ...with industry-standard debug tools (e.g., Synopsys... ...Understanding of CPU/SoC micro-architecture.... ...silicon solutions that power the future of Google'...Worldwide- Responsibilities Lead verification planning and... ...sophisticated UVM environments,... ...and design specifications... ...stimulus quality, and debug methodologies for... ...Mentor junior engineers in verification... ...years of ASIC/SoC verification experience... ...with low‑power verification, CDC...Permanent employmentTemporary workLocal area
$151k - $251.8k
...Responsibilities As a Design Verification Engineer, you will contribute... ...interconnect IPs that power next‑generation... ...the needs of complex SoC designs. Play a role... ...code and spec reviews, debugging functional failures from... ...skills in System Verilog, UVM Experience with Git...Hourly payFull timeRelocation- Dexian is seeking a Post-Silicon Validation Engineer for a 6+ month project in Austin, TX. The ideal candidate will have 2-6 years... ...experience in Pre/Post-Silicon Validation and be skilled in debugging SoC address/data hub subsystems. Key qualifications include strong...
- Renesas is seeking a SoC/IP Verification Engineer for our Infrastructure Power team in Austin, TX, where we... ...-located in our Austin design center. You will work alongside... .... Create and support UVM compliant test-bench... ...top-level environments Debug tests in collaboration with...Work experience placement
- ...UMC team is looking for an ASIC Design Verification Engineer to join our growing team. We develop... ...leading‑edge DDR technologies powering data center and machine learning... ...and directed) using SystemVerilog/UVM/SystemC. Triage and debug regressions. Analyze code and functional...
AMD
Austin, TX10 hours ago - ...companies in the world to find a verification engineer to help verify their complex... ...forefront of innovation in design verification, where you'll... .... Requirements Strong debugging and analytical capability, able... ...expertise in SystemVerilog and UVM, including stimulus...
Platform Recruitment
Austin, TX10 hours ago - ...Overview Position: Design Verification Engineer (Einfochips) Location: Austin, TX and San Jose, CA What... ...C++ At-least 6+ year of experience in UVM Experience in complete verification cycle... ...bench, stress/corner testing, failure debug, gate level simulations, assertions,...Full timeTemporary workWork at officeRemote work
Arrow Components Corp
Austin, TX10 hours ago $125 - $135 per hour
...are seeking a highly skilled Design Verification Engineer to join our team. The... ...creating testbenches, and debugging complex GPU designs to ensure... ...languages such as System Verilog, UVM, and C++ to verify GPU... ...functionality, performance, and power consumption. You ensure...Contract workBayOne Solutions
Austin, TX11 hours ago- ...Technologies group, you'll help design and manufacture our... ..., high-performance, power-efficient processor,... .... The DFT Design Verification Engineer will be on a team which... ...constrained random tests - Debugging failures, running gate... ...processors and/or GPU/SOC designs + Hands-on...
Apple
Austin, TX2 days ago - TSMC in Austin, TX is seeking a Power Management design and verification engineer to join their PMIC design team. In this role, you will help define next-generation semiconductor technology, focusing on innovative PMIC products for Artificial Intelligence processors. The...
- Overview TSMC’s Power Management Research and Design Department, in Austin, TX, is looking for an exceptional Power Management design and verification engineer to work as part of the PMIC design team. Responsibilities In this role, the candidate will be part of the engineering...
- ...implementing the digital chip SOCs for communications via... ...a state of the art verification environment to... ...SystemVerilog Work with the design and communication... ...benches constructed using UVM Develop a highly... ...Electrical / Communications Engineering or Computer Science,...Permanent employment
- ...Advisor with extensive experience in AMS Verification. The ideal candidate will have 10-15... ...strong grasp of analog and mixed signal design. Responsibilities include leading verification... ...’s degree in Electrical or Computer Engineering is required, along with proficiency in...
- ...has been propelled by the top engineers in mixed-signal processing.... ...career! Join our silicon design verification team and work closely with digital... ...Testbench development using UVM methodologies. Implement... ...simulations. Regression debug support and other flow/infrastructure...
- ...propelled by the top engineers in mixed-signal processing... ...join our Mixed-Signal Verification Engineering team to... ...with digital and analog designers, applications... ...to failure analysis, debug, and resolution efforts... ...HVLs) like SystemVerilog/UVM, Vera, or others. Solid...Full timeInternshipWork at officeRelocation
Do you want to receive more vacancies?
Subscribe and receive similar vacancies to SoC Design Verification Engineer | UVM & Power Debug. Be the first to apply!
Related searches
- manufacturing design engineer Austin, TX
- lead product engineer Austin, TX
- rtl design engineer Austin, TX
- digital design engineer Austin, TX
- product design engineer Austin, TX
- director of product engineering Austin, TX
- senior software design engineer Austin, TX
- sr. product engineer Austin, TX
- cad design engineer solidworks Austin, TX
- chief design engineer Austin, TX