Manager Digital Engineering 2

RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: Yes CLEARANCE TYPE: Secret TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. Northrop Grumman Mission Systems (NGMS) Sector has an immediate opportunity available for a Manager, Digital Engineering 2 located in Linthicum, MD. What You’ll Get To Do The Manager Digital Engineering 2 will focus on two primary areas of responsibility: people leadership and technical performance.Direct reports will include design engineers (T1 – T4) as well as staff and sr. staff engineers.Team leadership will include functional oversight of a group of 10‑15 engineers comprised of mainly FPGA/Firmware/digital design engineers working on multiple programs, IRAD initiatives, and new business capture opportunities.Responsibilities include support and adherence to standard design processes, oversight of cost, schedule, and technical quality for various development, integration or production programs, and support for new business development and proposals.An additional critical responsibility is the development and advancement of the FPGA technology, including driving new design processes and determining more efficient methodologies for design. Roles & Responsibility Responsible for staffing and workload forecast; employee inclusion, engagement, mentoring and career development; employee training and identification and training of skills required to execute on programs. The responsibilities include the recruiting, sourcing, onboarding, performance management and contract maintenance for the contractors working in the business area. Maintain positive relationships with internal and external stakeholders. Build diverse and inclusive teams with high levels of engagement, including mentoring and coaching. Leverage a portfolio with combined interpersonal, business and technical capabilities. Collaborate with Digital Management peers both in the FPGA Design 2 Section as well as the Digital Management across the Digital Technologies Department. Operate in a team environment and collaborate across the business sector with varying levels of leadership to set and exceed program goals. Champion change within the organization, to achieve competitive advantage for the business. Basic Qualifications Bachelor’s degree in Computer Engineering (BSCE), Electrical Engineering (BSEE) or related STEM Degree with 8 years of related experience or a Master’s degree with 6 years of related experience or a PhD with 4 years of related experience. U.S. Citizenship is required. Must have a Current/Active DoD Secret Clearance. Secret Clearance is required to start. Must be able to obtain Special Program Access (SAP). An Active Secret Clearance and Special Program Access (SAP) are required for continued employment. Must have 5 years experience in management or lead of employees and/or management of a project. Must have 8 years experience in all areas of the Digital/FPGA Design process, from requirements analysis through verification testing. Must have 5 years experience with designing, leading and managing FPGA design projects. Preferred Qualifications Master’s degree in Computer Engineering (MSCE), Electrical Engineering (MSEE) or related STEM Degree. Active DoD Top Secret or higher clearance. Experience leading teams in a multi-disciplined engineering environment. Experience leading/managing FPGA, ASIC, SoC, and/or digital subsystem design projects. Knowledge of current digital technologies (FPGA, ASIC, SoC, verification, and/or subsystem). Demonstrated proficiency in mentoring and the ability to build highly engaged teams. Excellent verbal and written communication skills and the ability to present knowledge to a wide variety of audiences of different backgrounds effectively. Primary Level Salary Range: $153,800.00 - $230,800.00 The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions. Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, company paid holidays and paid time off (PTO) for vacation and/or personal business. The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates. Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions. #J-18808-Ljbffr