Senior ASIC CAD Engineer: Frontend to Tapeout Power & STA
Palo Alto Networks
Palo Alto Networks, Inc. is seeking an experienced ASIC CAD Engineer in Santa Clara, California. In this role, you will be the vital link between front-end logic and design teams, focusing on Logic Synthesis, Static Timing Analysis, and Power Optimization. The ideal candidate has over 10 years of experience and expert-level scripting skills. Join a pioneering team committed to innovation and excellence while driving the future of cybersecurity solutions. #J-18808-Ljbffr Palo Alto Networks, Inc.
Vacancy posted 1 day ago
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