Analog IC Design and Verification Engineer

Analog IC Design and Verification Engineer Fremont, California, United States We are creating devices that enable a bi‑directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description The Brain Interfaces SoC Department delivers chip architecture and silicon implementation of neural recording and stimulation system‑on‑chip (SoC) for high‑bandwidth brain‑machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. Job Description and Responsibilities The engineer will be responsible for analog and mixed‑signal chip design, from circuit design to layout and verification. Other responsibilities include: Design analog circuit building blocks and subsystems in transistor‑level to achieve a variety of challenging noise, mismatch, distortion, power consumption, and cost requirements while satisfying top‑level specifications Work with layout teams to oversee block‑level layout of multiple blocks Plan and execute analog verification plan for a portion of IP or chip and run complex simulations and analyses (e.g., power, performance, linearity, yield) on designs Design, program, and run complex tests and review tests of junior team members; ensure bugs and other issues are identified and appropriately analyzed Consult with internal or external users and third‑party vendors to guide implementation and ensure alignment with their needs and goals Required Qualifications Bachelor of Science degree and at least 5 years of experience in a related technical field after receiving the BS degree Minimum 5 years of experience in analog/mixed‑signal integrated CMOS circuit design for a specific area (e.g., delta‑sigma ADC, SAR ADC, DAC, VCO, PLL, DLL, Audio CODEC, Class D audio amplifier, high‑speed PHY & SERDES) with a successful track record of silicon validation The ideal candidate is enthusiastic about building things, highly analytical, and enjoys tackling new problems regularly Preferred Qualifications Masters or PhD in electrical engineering, physics, or other related fields Experience with design for high‑volume production Experience in lab testing of high‑precision analog and mixed‑signal ICs Functional modeling experience and logic verification with Verilog AMS and SystemVerilog Experience in design and layout with advanced CMOS FinFET technologies Skills in scripting and automation for complex simulation scenarios Expected Compensation The anticipated base salary for this position is within the following range. Your actual base pay will be determined by your job‑related skills, experience, and relevant education or training. In addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full‑time employees. Base Salary Range: $125,000 - $291,000 USD What We Offer An opportunity to change the world and work with some of the smartest and most talented experts from different fields Growth potential; we rapidly advance team members who have an outsized impact Excellent medical, dental, and vision insurance through a PPO plan Paid holidays Meals provided Equity (RSUs) Temporary Employees & Interns excluded 401(k) plan Interns initially excluded until they work 1,000 hours Parental leave Temporary Employees & Interns excluded Flexible time off Temporary Employees & Interns excluded #J-18808-Ljbffr