Design Verification Engineer-System Verilog/UVM

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE:As a member of the Front-End Verification team, you will play a critical role in validating the functional correctness of next-generation AMD/Xilinx programmable devices. Working across a multi-site, global engineering organization, you will drive high-quality verification execution from feature definition through silicon readiness.THE PERSON:You are passionate about digital design and advanced verification methodologies. You thrive in collaborative, cross-functional environments and communicate effectively across sites and time zones. With strong analytical and problem-solving skills, you take ownership of complex technical challenges and are motivated to continuously learn and improve.KEY RESPONSIBILITIES:  Collaborate with architects, hardware and firmware engineers to understand the new features to be verified Take ownership of block level verification tasksDefine test plans, test benches, and tests using System Verilog and UVMDebug RTL and Gate simulations and work with HW and SW development teams to verify fixesReview functional and code coverage metrics to meet the coverage requirementsDevelop and improve existing verification flows and environmentsPREFERRED EXPERIENCE:  Strong understanding of computer architecture and logic designKnowledge of Verilog, system Verilog and UVM is a mustStrong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verificationWorking knowledge of C/C++ and Assembly programming languagesExposure to scripting (python preferred) for post-processing and automationExperience with gate level simulation, power and reset verification  ACADEMIC CREDENTIALS:  Bachelors or Masters degree in computer engineering/Electrical Engineering or a related fieldLOCATION: San Jose, CA #LI-RL1#LI-HYBRIDThis role is not eligible for visa sponsorship.Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.