STA Design Engineer - Timing Signoff & Automation
NXP Semiconductors
NXP Semiconductors in the United States is seeking an experienced ASIC Timing Analyst responsible for end-to-end timing signoff, constraints creation, and validation across frontend, IP, DFT teams to ensure timing closure for flagship SoCs. You will work with implementation owners and Full-Chip STA teams, generate timing fixes, and drive automation strategies to improve scalability and design quality. Strong knowledge of Synopsys STA tools, scripting in Python/TCL, and experience with advanced #J-18808-Ljbffr NXP Semiconductors
Vacancy posted 1 day ago
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