Chip-Design FE Engineer: RTL, Synthesis & Timing
Apple Inc.
Apple Inc. in Austin, Texas, is seeking an experienced hardware engineer to optimize and implement chip designs for cutting-edge devices. The role focuses on synthesis, timing constraints, power integrity, and signoff, ensuring robust physical design across FPGA/ASIC-like workflows. You will collaborate with CAD teams to resolve issues, apply ECOs, and push for low power, small area, and high-performance results while maintaining RTL validity and verification using industry-standard tools. #J-18808-Ljbffr Apple Inc.
$136k - $218.5k
...looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic and growing... ...level, cluster level, and/or full chip level.Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning...SuggestedFull time$180k - $245k
...are looking for a Senior Design Engineer to design, integrate, and sign off RTL for blocks across our... ...the compute fabric's on-chip interconnect and memory... ...microarchitecture spec through clean, synthesis-ready RTL, working... ...write and maintain SDC timing constraints, and analyze...SuggestedNight shift- ...Technology Solutions is seeking an experienced Physical Design Contractor in Austin, TX to drive synthesis, floorplanning, and PPA optimization for large, timing-critical designs. You will work closely with RTL and external teams to ensure design quality and timing targets...SuggestedFor contractors
- ...Whether you’re designing next-gen processors,... ...seeking a highly motivated RTL IP Design Engineer to join AMD's Security... ...across AMD System-on-Chip (SoC) products spanning... ..., including lint, timing, DFT, DFP, and other... ...simulation, debug, linting, synthesis, timing analysis, and...Suggested
- ...group, you would help design and manufacture the next... ...efficient processor system-on-chip (SoC) that powers Apple... ...teams to deliver RTL and specifications for... ...other Apple teams. Close timing, power, area, and lint... ...: logic optimization, synthesis, timing analysis, floor...Suggested
$108k - $172.5k
...for a motivated ASIC Physical Design & Timing Engineer to join our multifaceted and... ...for the physical design, synthesis, place and route feasibility... ...netlist convergence for all chips within NVIDIA. Drive physical... ...architecture and/or background in RTL/logic design and/or skills...$120k - $200k
...Reconfigurable Dataflow Unit) — a chip built on a dataflow... ...efficiency, and faster time to value. About the team The RTL design team builds the compute... ...role SambaNova RTL Design Engineers design component units of... ...Experience with digital logic synthesis tools and static timing...Full timeTemporary workLocal areaWorldwideFlexible hours- ...an excellent full-time/permanent role giving... ...of digital design, verification, debug... ...to industry leading chips. Job Duties Develop... ...mentor for junior engineers. Represent digital... ...backend design flow (synthesis / STA / P&R) Full... ...micro-architecture, RTL implementation, backend...Permanent employmentFull timeWork experience placement
- ...future. Whether you’re designing next-gen processors, enabling... ...ROLE:We are seeking an RTL Power Design Specialist... ...for System-on-Chip (SoC) products across all... ...innovative and analytical engineer who is passionate about... ...simulation, linting, synthesis, power-aware verification...
- ...the future. Whether you’re designing next-gen processors, enabling... ...your career.THE ROLE:As an RTL Methodology Engineer, you will have a unique... ...design workflows including synthesis, verification, physical design, place and route, and timing closureStrong problem-solving...Work at office
- ...the future. Whether you’re designing next-gen processors, enabling... ....THE ROLE:As a CPU Core RTL Design Engineer, you will help design and optimize... ..., power, area, and timing requirements.KEY RESPONSIBILITIES... ...design verification, synthesis, timing closure, and physical...
- ...advance your career. THE ROLE:As a CPU Core RTL Design Engineer, you will help design and optimize... ...to balance performance, power, and timing considerations in modern processor design... ...design verification, synthesis, timing closure, and physical design effortsDebug...
$164.47k - $311.89k
...our team, you will help design the next generation of... ...individual who is hands-on with RTL implementation for... ...a CPU RTL Logic Design Engineer your responsibilities... ...integration in full chip designs.• Participates... ...performance, area, and timing goals as well as design...Full timeWork experience placementInternshipLocal areaImmediate startShift work- ...group, you’ll help design and manufacture... ...of strategic engineering along with... ...design and large chip integration, being... ...design from RTL to tapeout.... ...closely with the FE team to understand... ...physical design, synthesis, DFT or... ...all aspects of timing, electrical and...Temporary work
- ...career. THE ROLE: As a CPU Core RTL Design Engineer, you will help design and optimize next... ...to balance performance, power, and timing considerations in modern processor design... ...Support design verification, synthesis, timing closure, and physical design efforts...
$200k - $275k
...We are looking for a Lead RTL Design Engineer to own microarchitecture definition... ..., memory subsystem, on-chip interconnect/NoC, low-power... ...from architecture spec through synthesis-ready RTL, collaborating... ...blocks regularly, review area/timing/power reports, and make data...Night shift$168k - $264.5k
...are looking for a Full-Chip RTL Integration Engineer to join our dynamic and growing FE-ASIC development team.... ...SoCs while ensuring design quality, verification... ...including lint, CDC, RDC, synthesis, and connectivity... ...US, CA, Santa Clara; US, TX, AustinType: Full timeFull time$180k - $255k
...Reconfigurable Dataflow Unit) — a chip built on a dataflow... ..., and faster time to value. About the... ...seeking a Principal Engineer to own the design, integration, and... ...microarchitecture definition through RTL and integration of... ...lint, CDC/RDC, synthesis, timing constraint...Full timeTemporary workLocal areaWorldwideFlexible hoursNight shift- ...are seeking an experienced engineer for SoC Static Timing Analysis for advanced semiconductor... ...Analysis across complex designs, driving initial... ...implementation engineers from synthesis through final timing closure... ...Implementation owner(s) and Full Chip STA team to close...Full timeWork at officeLocal area
$178.85k - $218.59k
...tomorrow across every market segment of chip design, including artificial intelligence,... ...world a better place, one processor at a time. Are you ready? To learn more about... ...Description:The RoleAs a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team...Full timeWork experience placement- ...career. THE ROLEWe are looking for an RTL Design Engineer to join our growing Memory Controller... ...and code reviewsPerform lint, CDC, and timing analysis to support high-quality design... ..., including simulation, lint, and synthesis, is preferredExperience with digital logic...
- ...Pittsburgh, PA and Austin, TX) seeks a senior RTL design engineer to own block level design, integration and... ...should bring strong Verilog or SystemVerilog, timing closure and low‑power techniques, plus familiarity with on‑chip interconnect and memory interfaces. Work...
- ...We are looking for a Physical Design Engineer with strong expertise in... ...Area (PPA) optimization, and timing convergence for advanced technology... ..., placement, clock tree synthesis (CTS), routing, and physical... ...and closure. Collaborate with RTL, DFT, STA, and Signoff teams...
- ...Inc. in Austin, TX is seeking a qualified engineer to write SystemVerilog RTL for GPU microarchitecture, perform synthesis, timing analysis, and collaborate with verification... ..., strong SystemVerilog, CAD tools, and GPU design experience, plus Perl/Python scripting. 40...
$100k - $180k
Physical Design Engineer (PnR / PPA / Timing Closure) Job Description Job Title: Physical Design Engineer (PnR... ...planning, placement, clock tree synthesis (CTS), routing, and physical verification... ...and closure. Collaborate with RTL, DFT, STA, and Signoff teams to ensure...Minimum wageLocal area- Design · San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX · Senior level A senior RTL design engineer typically owns block level design, integration,... ...Verilog or SystemVerilog, timing closure, and low power... ...plus familiarity with on chip interconnect and memory...Work at office
$100k
...all seniorities.Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon... ...standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts...Permanent employment$185.2k - $250k
...implementing the digital chip SOCs for... ...responsibilities • Work with RTL/logic designers to drive... ...implementation through synthesis, floor planning, bus... ...congestion analysis, timing closure, IR drop analysis... ...other physical design engineers as well as with the RTL...Permanent employmentFlexible hours- ...TX is seeking an ASIC clock engineer to own the clock domain across GPU/CPU design. You will optimize PPA,... ...evaluate clocking topologies in RTL, and work with floorplanning and timing teams to enable high-speed... ..., and clocking in advanced chips. #J-18808-Ljbffr NVIDIA
$168k - $264.5k
...looking for a Senior CPU Design Methodology Engineer!The complexity of chip development has greatly increased... ...SOC design automation, RTL integration, and chip... ...languagesExperience in synthesis and physical design is a... ...Austin; US, AZ, Remote; US, CA, Santa ClaraType: Full timeFull timeRemote work
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