SoC STA Design Engineer - Timing Signoff Lead
NXP Semiconductors NV
NXP Semiconductors in Austin, TX seeks an experienced SoC STA engineer to own end-to-end timing signoff across complex designs. You will drive constraint creation, validate with frontend, IP, and DFT teams, and collaborate with implementation to close timing at advanced nodes. The role emphasizes scripting (Python, TCL, Perl) for timing ECOs, AI-assisted automation, and continuous methodology improvements to boost design quality and productivity. #J-18808-Ljbffr NXP Semiconductors NV
- ...seeking an experienced ASIC Timing Analyst responsible for end-to-end timing signoff, constraints creation,... ...closure for flagship SoCs. You will work with implementation... ...owners and Full-Chip STA teams, generate timing... ...improve scalability and design quality. Strong...Suggested
$106.5k - $162k
...of Role As a Sr. Physical Design Engineer, you will be responsible for... ...floorplan, place and route, CTS, STA, and signoff. You will be reporting to... ...envelope for the world’s leading semiconductor company. We... ...& Route Implement ECOs for timing closure Signal EM/Noise and...SuggestedWork at office- ...are seeking an experienced engineer for SoC Static Timing Analysis for advanced semiconductor... ...Analysis across complex designs, driving initial... ...early stages to final Timing Signoff for cutting-edge technology... ...Implementation owner(s) and Full Chip STA team to close TimingTiming...SuggestedFull timeWork at officeLocal area
- ...enabling human life on Mars.SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)At... ..., place and route, timing, noise, physical verification... ...logic equivalency and other signoff checks)Develop/improve physical... ...in static timing analysis (STA), noise, logic equivalency,...SuggestedPermanent employmentWorldwideWeekend work
- ...SoC Physical Design Engineer, PnR Imagine what you could do here! At Apple, new... ...collaborating with architecture, CAD, timing and logic design teams,... ...(PnR), power grid, timing (STA), physical design... ...verification, and driving the signoff closure for the partitions....SuggestedInternship
- ...features. As a Staff Engineer Timing Methodology, you... ...our cutting-edge designs into silicon reality... ...convergence at SOC level as well. Responsibilities... ..., including Signoff to build timing... ...advancements in STA and new process... ...000.00 1 week ago Lead Physical Design Engineer...Full timeSummer internship
$100k
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing... ...mid- to senior-level Physical Design Engineer with a strong background in static timing analysis (STA). In this role, you will help... ...teams through final signoff and tapeout.This role is...Permanent employment$136k - $218.5k
...looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic and growing team.... ...low-power NVIDIA CPUs, GPUs, LPUs and SoCs at block level, cluster level, and/or... ...synthesis, routing, physical optimization, signoff, and ECOs.Demonstrated success...Full time- Austin, TX Title: Static Timing Analysis (STA) / Timing Closure & Signoff Engineer Function: Physical Design - Timing Signoff Experience: 3 - 8 years of relevant STA... ...experience Engagement: Engineering services for a leading global SoC (System-on-Chip) manufacturer Location:...Full time
$112k - $168k
...TitleStaff Applications Engineer - Timing & SignoffJob ID18506... ...We deliver industry-leading silicon design, IP, simulation and... ...foundry, look at their STA violations or EMIR... ...of view on what good signoff looks like, and you are... ...working on advanced node SoCs and 3DICsEngage...Day shift- ...experienced candidate to lead Front End Design projects. This is... ...highly motivated engineer with a passion for... ....Verification & Signoff:Oversee pre-... ...IP creation and/or SoC and IP (CPU, Memory... ...and support PD and STA teams.*Experience... ...’t.SummaryLocation: AUSTINType: Full timeFull time
$108k - $172.5k
...looking for a motivated ASIC Physical Design & Timing Engineer to join our multifaceted and growing team... ...and route feasibility analysis, timing/STA, & netlist convergence for all chips... ...frequency and low-power hardware (CPUs, GPUs, SoCs, etc.) at block level, cluster level,...- Wipro Limited in Austin, Texas is seeking a Physical Design Engineer with strong PnR, PPA optimization, and timing convergence to drive block-level design from... ...closure across advanced nodes, collaborating with RTL/STA/Signoff teams to tape out complex silicon. The role...
$100k - $180k
Physical Design Engineer (PnR / PPA / Timing Closure) Job Description Job Title: Physical Design Engineer... ...WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting... ...maintain timing constraints (SDC) and STA signoff methodologies. Perform EMIR (...Minimum wageLocal area- SoC Physical Design Engineer, PnR job at Apple Inc.. Austin, TX. We are seeking a seasoned Physical Design... ...from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off... ...motivated to solve more challenging timing closure issues, area & power optimization...
- ...Austin, TX is seeking a Physical Design engineer to drive the netlist-to-tapeout flow for complex SOC partitions. You will collaborate with architecture, CAD, timing and logic design teams to meet... ...GDS2 implementation, and driving signoff closure while continually improving...
- Globex Digital Corp. seeks a Physical Design Engineer for Austin, TX to lead PnR/VLSI flow, floorplanning, CTS, routing, and timing convergence. You will optimize Power-Performance... .... You will collaborate with RTL, DFT, STA, and Signoff teams to drive tapeout readiness and...
- ...Synopsys is the leader in engineering solutions from... ...We deliver industry-leading design, verification, and signoff solutions that power... ...advanced nodes and complex SoCs, we partner with... ...and accelerate time-to-market. You... ...static timing analysis (STA), power integrity (...
$152.36k - $210k
...Technologies, Inc. Job Area Engineering Group, Engineering... ...This individual leads, plans,... ...responsibility of the Physical Design Flow of high-speed... ...-architecture, SOC algorithm design... ...and Route, PDN, Timing analysis and... ...effort to drive to signoff closure for tapeout...- ...are continuing to enable leading technology companies... ...market segment of chip design, including artificial intelligence... ..., one processor at a time. Are you ready? To... ...of choice for SOC designs across a broad... ...others and a belief that engineering is a team sport.Knowledge...Full time
$100k
Tenstorrent is leading the industry on cutting... ...talented Physical Design Engineers to implement high-... ...-leading AI SOC. You'll own the complete... ...(e.g. I3C, UART), signoff breadth (DRC/LVS,... ..., PNR, and STA for assigned partitions... ...including power intent, timing, and physical...Permanent employment$128.6k - $217.2k
Senior Physical Design... ...Established in 1997, our leading-edge technologies... ...Physical Design Engineer to drive Advanced... ...verification (PV) signoff for high-... ...front-end design, STA, IR/EM, and verification... ...teams to close timing, power, and... ...) for complex SoCs or IP.Strong...Temporary workWork at officeWork from home- Position:Physcial Design EngineerJob... ...synthesis, PNR, and STA for assigned... ...designers, and DFT engineers to resolve implementation and signoff issues across your... ...synthesis, PnR, timing convergence and... ...System-on-Chip (SoC) design and... ...Fortune #133), is a leading global provider...Full timeWork at office
- ...Computing & Graphics (CG) SoC Architecture team, you will develop and design custom silicon for... ...you will work with the lead SoC architect to define... ...located in across multiple time zones and geographies. You... ...workers, teams, and customer engineering teams.KEY...
$143.15k - $265.85k
Staff Digital Design Engineer - SOC Low Power, Clocking & Integration page is loaded## Staff Digital... ...660Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless... ...RDC), synchronization techniques, and timing considerations.* Extensive experience...Flexible hoursShift work$225k - $350k
...a Principal ASIC Design Engineer, you will take a leadership... ...s inference ASICs/SoCs. You will own the... ...through RTL signoff, collaborating... ...Ownership & Signoff: Lead lint, CDC/RDC, DFT... ...on floorplan and timing closure. Own... ...lint, CDC, synthesis/STA, DFT) using major...Flexible hoursNight shift$154k - $286k
...ResponsibilitiesTechnical Expertise: Lead technical... ...of Cadence signoff portfolio. Work closely with design teams to meet customer... ...of Cadence’s timing signoff & closure and... ...with R&D and Product Engineering to influence tool... ...sigoff & closure, STA, IR Drop, and power...Full time- ...an experienced Digital Designer for SoC Implementation / Physical... ...& route, CTS, routing, STA, PDN, PDV and signoff.Drive timing, power, IR/EM, and physical... ..., and tool innovation.Lead adoption of advanced node... .../ Electronics Engineering or related field10+ years...Full timeWork at officeLocal area
$180.2k - $270.4k
...a Sr Staff Physical Design PPA Engineer. you will be responsible... ...You will lead PPA initiatives by identifying... ...an IP block through signoff flows, including timing and physical... ...RTL counterparts and SOC teams to resolve design... ...latest industry P&R/STA flows and tools ~...Hourly payFull timeRelocation- ...Bay Area, Pittsburgh, PA and Austin, TX) seeks a senior RTL design engineer to own block level design, integration and sign-off for complex SoC components. You should bring strong Verilog or SystemVerilog, timing closure and low‑power techniques, plus familiarity with on...
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