Senior Principal DFT Architect: SoC Test & Verification
$196k - $364kCadence Design Systems Inc
Cadence Design Systems is seeking a motivated hardware engineer for the Modus R&D team. You will design and implement advanced Design-for-Test (DFT) solutions for the semiconductor industry. Responsibilities include developing test fabrics and overseeing project execution, while mentoring engineers across locations. The role offers an annual salary range of $196,000 to $364,000 and includes a comprehensive benefits package, ensuring you receive equity and incentive compensation. #J-18808-Ljbffr
Vacancy posted 1 day ago
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