Verification Engineer

What you do at AMD changes everything At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Join us as we shape the future of AI and beyond. The Role As a verification engineer in the AECG Group, you will help bring to life cutting‑edge FPGA and ASIC IP for a variety of target customers. As a member of the front‑end design/integration team, you will work closely with the architecture, IP design, product development teams, and product engineers to achieve first‑pass silicon success. The Person You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem‑solving skills and are willing to learn and ready to take on problems. Key Responsibilities Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified. Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases. Code IP or SS level UVM‑based testbenches, verification components – monitors, scoreboard, checkers. Build the directed and random verification tests. Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality. Preferred Experience Experience in IP level ASIC verification. Experience in Verilog, SystemVerilog, Object‑Oriented programming. Developing UVM based verification frameworks and testbenches. Scripting and automation of verification processes and flows. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process. Good Computer Architecture and systems knowledge. Comfortable in Python / Perl and editing/maintaining scripts. Exposure to leadership or mentorship is an asset. Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape‑Out. Experience with PCIe, CXL, NVMe or Ethernet protocols. Strong communication skills and ability to work independently as well as in a cross‑site team environment. Academic Credentials Bachelors or Masters degree in Computer Engineering / Electrical Engineering. Location San Jose, CA San Diego, CA Austin, TX Longmont, CO Visa Sponsorship This role is not eligible for visa sponsorship. Benefits Benefits offered are described: AMD benefits at a glance. Equal Opportunity Statement AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AI Screening Disclosure AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. Existing Vacancy This posting is for an existing vacancy. #J-18808-Ljbffr