Logic Design Engineer, Mixed-Signal & High-Speed IO
AMD
AMD in Santa Clara, CA is seeking an adaptive design engineer for the mixed-signal high-speed IO team. You will develop Verilog RTL, create microarchitecture specs, and drive ASIC flows while collaborating with verification and physical design to ensure timing and silicon quality. The role requires strong analytical skills, initiative to drive tasks, and the ability to mentor junior engineers in a fast-paced environment. Visa sponsorship is not offered for this position. #J-18808-Ljbffr AMD
Vacancy posted 1 day ago
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