Senior ASIC Physical Design Engineer - San Jose, CA Hybrid

Location: San Jose, CA Hybrid



Duration: 12 Months



Employment Type: Contract

Position Overview

We are looking for a highly experienced Senior ASIC Physical Design Engineer to contribute to the development and implementation of high-performance semiconductor products utilizing advanced process nodes. The engineer will be responsible for activities spanning RTL synthesis, floorplanning, physical implementation, timing optimization, and PPA improvement for complex, timing-critical ASIC and SoC designs. This role requires close collaboration with architecture, RTL, physical design, and implementation teams throughout the silicon development lifecycle.

Key Responsibilities

• Perform RTL synthesis for complex ASIC and SoC designs using Cadence Genus , ensuring designs meet established implementation and performance objectives.
• Drive continuous power, performance, and area (PPA) optimization across synthesis and physical design stages.
• Create, evaluate, and refine floorplans in Cadence Innovus to achieve effective area utilization, congestion management, and routing efficiency.
• Work closely with RTL and architecture teams to identify timing, constraint, and implementation concerns and provide actionable feedback.
• Collaborate with physical implementation and place-and-route teams to support timing closure, design convergence, and overall implementation quality.
• Investigate timing violations and critical paths , determine root causes, and recommend architectural or implementation-level changes to improve timing convergence.
• Provide end-to-end support across the synthesis-to-physical implementation flow , ensuring design quality, performance, and project schedule targets are consistently maintained.

Required Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a closely related technical discipline .
• Minimum 5+ years of professional experience in ASIC or SoC Physical Design .
• Strong hands-on experience with Cadence Genus for RTL synthesis and Cadence Innovus for floorplanning and physical implementation .
• Demonstrated experience implementing large-scale, high-performance semiconductor designs with challenging timing requirements.
• Solid understanding of RTL synthesis, timing analysis, physical implementation, timing closure, and PPA optimization .
• Practical experience with advanced semiconductor process technologies , including 5nm, 3nm, or newer technology nodes .
• Strong verbal and written communication skills with the ability to effectively coordinate with RTL, architecture, physical design, and implementation engineering teams .

Preferred Qualifications

• Previous experience working on sophisticated SoC, AI, HPC, or accelerator architectures .
• In-depth understanding of timing closure techniques and synthesis-to-implementation correlation .
• Knowledge of modern physical implementation methodologies, design constraints, and physical optimization strategies .
• Experience working with globally distributed engineering organizations and coordinating across teams to successfully deliver production-quality silicon.

Thanks & Regards

Himanshu Sharma

Recruitment Manager

Email: View email address on us.fitly.work