Process Engineering Manager - CMP, Dice, Grind & Bonding

Position Summary The Process Engineering Manager - CMP, Dice, Grind and Bonding leads a team of process engineers and technical contributors responsible for wafer fabrication process development, sustaining, yield improvement, and technology transfer activities across assigned modules. This role provides senior technical and people leadership across chemical mechanical planarization, wafer dicing, grinding / thinning, wafer bonding, debonding, surface preparation, cleans, and related metrology in a cleanroom manufacturing environment. Primary Scope CMP, post-CMP cleans, wafer dicing, grinding, thinning, backgrind, wafer bonding, debonding, surface preparation, related metrology, process control, sustaining, development, qualification, and transfer. People Leadership Expectations Serve as the direct people leader for an engineering team, with accountability for team performance, engagement, development, and execution against business priorities. Set clear goals, priorities, and expectations for individual contributors; ensure employees understand how their work supports fab, customer, program, and business objectives. Provide regular coaching, feedback, recognition, and career development support for employees at varying levels of experience. Build technical depth across the team by creating development plans, supporting knowledge sharing, strengthening process ownership, and delegating meaningful technical ownership. Assess team capability, identify skill gaps, and partner with leadership, HR, and Talent Acquisition on workforce planning, hiring, onboarding, retention, and succession planning. Create a culture of accountability, collaboration, safety, technical rigor, continuous improvement, and respectful communication. Conduct performance management activities including goal setting, check‑ins, development discussions, performance feedback, and corrective action when needed. Develop future leaders by creating stretch assignments, mentoring high‑potential employees, and building a bench of capable process owners. Major Area of Accountability Lead process development, optimization, qualification, and sustaining activities for CMP, dice, grind, bonding, debonding, cleans, and associated metrology processes. Provide senior-level technical direction for CMP, slurry / pad selection, endpoint strategies, post-CMP cleans, wafer dicing, grind / thinning, wafer bonding, debonding, surface preparation, and related module‑level integration interactions. Drive process capability, yield improvement, defect reduction, surface quality, planarity, particle control, wafer strength, die quality, bonding integrity, void reduction, and cost‑of‑ownership initiatives. Lead root‑cause investigations and corrective actions for process excursions, yield limiters, defectivity issues, tool matching gaps, contamination concerns, wafer damage, bonding defects, and reliability risks. Apply structured problem‑solving methodologies such as 8D, 3D, Fishbone, 5 Why, fault‑tree analysis, and other formal root‑cause tools. Use DOE, SPC, process capability analysis, and statistical methods to improve process control, manufacturability, and long‑term stability. Partner with integration, device, product, equipment, quality, operations, reliability, and program teams to resolve complex technical issues and meet customer commitments. Guide new technology development, process transfer, process release, and qualification activities across CMOS, MEMS, photonics, photovoltaic, or heterogeneous integration / advanced packaging platforms. Establish and monitor key process metrics including yield, defect density, removal rate, non‑uniformity, dishing / erosion, surface roughness, die quality, wafer thickness, bonding strength, voiding, process capability, documentation health, and excursion response. Ensure compliance with safety, quality, documentation, change‑control, customer, and cleanroom operating requirements. Communicate status, risks, recovery plans, resource needs, and execution priorities clearly to senior leadership and cross‑functional stakeholders. Required Qualifications B.S., M.S., or Ph.D. degree in Mechanical Engineering, Electrical Engineering, Chemical Engineering, Materials Science, Physics, or another relevant engineering discipline. Minimum of 15 years of experience in a wafer fabrication cleanroom environment. Minimum of 2 years of leadership, supervisory, or management experience, preferably with direct people leadership responsibility. Experience as a process or area owner for at least two relevant process areas such as CMP, post‑CMP cleans, wafer dicing, grinding / thinning, wafer bonding, debonding, surface preparation, or related module processes. Experience working in CMOS, MEMS, photonics, photovoltaic, or heterogeneous integration / advanced packaging fabrication environments. Demonstrated experience leading structured problem‑solving efforts using 8D, 3D, Fishbone, 5 Why, fault‑tree analysis, or similar methodologies. Strong working knowledge of DOE, SPC, process capability analysis, and statistical methods, with the ability to teach and lead others in their application. Demonstrated ability to lead cross‑functional teams, manage multiple technical priorities, and deliver results in a fast‑paced manufacturing or development environment. Strong interpersonal skills with the ability to influence, coach, and develop engineers and technical staff. Excellent written and verbal communication skills. Demonstrated ability to meet commitments, manage multiple projects simultaneously, and shift priorities based on business needs. Passion for leading teams, developing people, and building strong engineering capability. U.S. Citizenship is required. This position will require the holding of, or ability to obtain, a government security clearance. Preferred Qualifications Experience with CMP consumables, slurry / pad selection, endpoint strategies, post‑CMP cleans, metal contamination control, or wafer surface preparation. Experience with wafer dicing, backgrind, wafer thinning, edge quality, chipping reduction, wafer handling, or die‑level defect reduction. Experience with wafer‑to‑wafer, die‑to‑wafer, fusion, hybrid, adhesive, eutectic, or temporary bonding processes. Advanced degree in engineering, materials science, physics, or a related technical field. Experience supporting both process development and production sustaining environments. Experience supporting government, aerospace, defense, or other high‑reliability customer programs. Experience with security‑sensitive manufacturing environments. Compensation & Benefits The annual salary range for this role is $136,960 - $205,440. Pay offered is based on many factors including, but not limited to, the job‑related experience, skills, education, and credentials of each candidate. SkyWater offers an exciting environment where the brightest semiconductor minds come together to achieve exceptional results. We offer competitive salary and an opportunity to participate in incentive plans as well other employee financial benefits including 401k match, life insurance and opportunities to purchase SkyWater stock at a discounted rate. Additionally, SkyWater offers a comprehensive benefits package which promotes a healthy life. This includes benefit eligibility day one, medical, dental, mental health benefits, vision, legal planning, short‑ and long‑term disability, paid time off, paid holidays, an on‑site fitness facility, and an on‑site self‑serve market. SkyWater complies with federal and state disability laws and makes reasonable accommodations for applicants and employees with disabilities unless doing so would cause an undue hardship. Alternative methods of applying for employment are available to individuals unable to submit an application through this site because of a disability. To request reasonable accommodations, to participate in the job application or interview process, to perform essential job functions, and/or to receive other benefits and privileges of employment, please contact Human Resources at View phone number on click.appcast.io or View email address on click.appcast.io. EOE, including disability/vets #J-18808-Ljbffr SkyWater Technology