Senior Design Verification Engineer - Physical AI Compute

About Velaura Velaura is building the next generation of compute platforms for Physical AI. As AI moves beyond the datacenter into robots, autonomous mobile systems, drones, and other embodied systems, traditional compute architectures are increasingly constrained by power, memory bandwidth, latency, real-time requirements, and functional safety considerations. Our mission is to develop the foundational compute technologies that enable intelligent systems to operate efficiently in the physical world. We are assembling a team of exceptional architects and engineers to rethink how AI, sensing, memory, and control interact within a modern computing platform. The Role We are looking for talented Design Verification Engineers to help verify and deliver Velaura’s next-generation Physical AI SoC. In this role, you will work closely with architects, RTL engineers, software engineers, and system teams to verify complex hardware blocks and system-level behavior across the entire platform. You will help establish confidence in the correctness, performance, reliability, and safety of the architecture—from individual RTL blocks to complete HW/SW systems running real-world workloads. We welcome engineers at all experience levels who enjoy understanding systems, finding corner cases, and solving challenging technical problems. Responsibilities Develop and execute verification strategies for key portions of the Velaura SoC. Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, and related methodologies. Collaborate with architects and RTL engineers to define verification plans, coverage goals, and correctness criteria. Verify compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other critical SoC infrastructure. Perform HW/SW co-verification involving firmware, drivers, runtime software, and operating system interactions. Verify performance, latency, bandwidth, QoS, and real-time system behavior under representative workloads. Develop assertions, checkers, scoreboards, and automated verification infrastructure. Participate in emulation, FPGA prototyping, and pre-silicon software bring-up activities. Drive bug investigation, root-cause analysis, and debug across hardware and software boundaries. Post-silicon debug and root cause analysis. Leverage modern engineering tools, including AI-assisted verification workflows, to improve productivity, quality, and coverage. Contribute to a culture of technical excellence and continuous improvement. Desired Experience 10+ Years of experience verifying complex digital systems. Strong analytical and problem-solving skills. Strong understanding of computer architecture, microarchitecture, SoC architecture and digital design fundamentals. Experience in understanding low power methodologies and verification criteria. Strong understanding of CDC issues, clocking and reset verification. Experience with SystemVerilog, UVM, C/C++, assertions, coverage-driven verification, and related methodologies. Familiarity with formal verification techniques and tools. Experience with emulation, FPGA prototyping, or pre-silicon validation environments. Understanding of memory systems, interconnect fabrics, caches, DMA engines, processors, or accelerator architectures. Experience debugging complex system-level issues. Ability to work effectively in a collaborative, multidisciplinary engineering environment. Relevant Backgrounds CPUs GPUs AI accelerators Networking and communications silicon Storage and data movement architectures Robotics and autonomous systems Automotive and ADAS platforms Aerospace and defense systems Real-time and safety-critical computing Functional safety architectures and methodologies Functional Safety Experience Experience with one or more of the following standards is a plus: ISO 26262 IEC 61508 IEC 61511 ISO 13849 Nice to Have Experience with AI, machine learning, or edge AI hardware. Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems. Experience verifying QoS, latency-sensitive, or real-time systems. Experience with HW/SW co-verification and system-level validation. Exposure to performance modeling, profiling, and workload characterization. Experience using modern AI tools and workflows to accelerate engineering productivity. Compensation & Benefits At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a competitive base salary, performance-based incentives, and equity participation, allowing team members to share in the company’s long‑term success. The base pay range for this role is between $200k and $500k, and your base pay will depend on your skills, qualifications, experience, and location. In addition to compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage, paid time off, flexible work arrangements, professional development opportunities, and other benefits designed to support the well‑being and growth of our team. Velaura is committed to pay equity and transparency, and we regularly benchmark compensation to ensure we remain competitive in the market. Why Velaura? This is an opportunity to help build a new class of computing architecture at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders and architects who have delivered industry‑defining products across mobile, cloud, and AI platforms. If you enjoy building hardware, tackling difficult technical challenges, and helping shape the future of Physical AI, we would love to hear from you. #J-18808-Ljbffr