RISC-V SoC Verification Lead
JDWK
A leading technology company in Austin, TX is seeking a Design Verification Engineer to own the verification environment for a RISC-V based SoC. You will architect and develop the verification framework, collaborating with design and software engineers to ensure the quality of both hardware and software. This position demands strong expertise in SystemVerilog/UVM and experience with regression testing in a fast-paced, startup environment. Join a small, agile team dedicated to innovative silicon development. #J-18808-Ljbffr JDWK
Vacancy posted 9 hours ago
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