Chip Lead & Physical Design Director: SoC PPA Mastery
Cadence
Cadence is seeking experienced Physical Design Architects to join our Performance Solutions Group in Austin, Texas. The ideal candidate has over 15 years of industry experience, with strong knowledge of digital design fundamentals and expertise in PPA optimization. You will drive complex customer SoC projects from RTL to GDS, collaborating with stakeholders and promoting internal initiatives. Familiarity with Cadence tools and scripting languages is essential. Join us to innovate in cutting-edge AI, automotive, and data center markets. #J-18808-Ljbffr Cadence
Vacancy posted 5 days ago
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