Design Verification Engineer

Design Verification Engineer

Immediate need for a talented Design Verification Engineer. This is a Fulltime opportunity with long-term potential and is located in San Francisco, CA (Onsite).

Key Requirements and Technology Experience:

• 6+ years of experience with verification concepts and architectures for complex digital and mixed-signal circuits
• Experience verifying designs at the block and system levels.
• Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)
• Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog / mixed-signal circuits
• Experience using SystemVerilog and advanced verification concepts and methodologies (UVM, SVA)
• Experience with Synopsys, Cadence, and Mentor simulations tools
• Demonstrated ability to plan and deploy complex, reusable, and scalable verification environments
• Experience with Perl/Python and Tcl or other scripting languages
• Experience with version control systems (DesignSync, git)
• Superior writing, grammar, and verbal communication skills
• Excellent problem solver; develops and employs automated processes where applicable
• Worked independently and in a global team and dynamic environment in a highly visible role
• Possesses ability to learn and adapt to new tools and methodologies on the fly
• Must have legal authorization to work in the US.
• BS in Electrical Engineering / Computer Engineering and 8+ years of related experience or an MS in Electrical Engineering / Computer Engineering and 6+ years of related experience.