Lead SoC Design Engineer - Edge AI, High-Performance ASIC

Job Description

Job Description

Lead SoC Design Engineer - Edge AI, High-Performance ASIC

Job Title: Lead SoC Design Engineer - Edge AI, High-Performance ASIC
Job Location: San Francisco, CA or Los Altos, CA - hybrid
Compensation: $300K - $400K base DOE plus equity
Requirements: SoC Microarchitecture, RTL Design, IP Integration (UCIe, DDR, CPU/GPU/NPU), ARM Cores, Memory Subsystems, AMBA Protocols (CHI, AXI, ACE, APB), HPC / Edge AI SoC

Position Overview
We're a well-funded, stealth startup building a next-generation, end-to-end computing platform powered by a custom, high-performance edge SoC on an advanced process node. By integrating flagship compute IP into an industry-leading design, we are building the optimized silicon foundation for our software platform from the ground up.

We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop the microarchitecture, own the critical tradeoffs required to hit aggressive PPA targets, and spearhead the implementation of key subsystems.

Key Responsibilities

 

• Microarchitecture: Author detailed microarchitecture documents and drive reviews with software, architecture, and verification teams.
• Drive PPA targets: Since we are developing a power-sensitive client product, you will drive performance/power tradeoffs using a data-driven approach to hit aggressive targets.
• Partner with the verification team: Participate in reviews of verification and emulation test plans to ensure successful first-pass silicon.
• RTL design: Own RTL coding, Lint/CDC/RDC checks, SDC and VCLP checks, and ensure that the design can be taken through physical design to meet frequency and power requirements.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; advanced degree preferred.
• 10+ years of experience in developing complex ASICs in advanced nodes.
• Deep knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AXI-S/APB)
• Experienced with Verilog, SystemVerilog, SystemVerilog Assertions (SVA).
• Proficiency in writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints.
• Experience with industry-standard ASIC CAD tools for simulation, synthesis, STA, Lint, LEC, CDC, RDC, and power estimation.

• Experience designing with multiple power domains and UPF.

  Preferred Qualifications

• Experience with commercial IP integration, ranging from high-speed interfaces (UCIe, DDR) to processing subsystems (CPU, GPU).
• Experience working directly with ARM cores and subsystems.
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Benefits

• Medical/Dental/Vision benefits
• Vacation/PTO
• 401K
• Equity
• Flexible Work Arrangements 

- For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.This job was first posted by CyberCoders on 07/08/2026 and applications will be accepted on an ongoing basis until the position is filled or closed. Everforth CyberCoders is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, sexual orientation, gender identity or expression, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, status as a crime victim, disability, protected veteran status, or any other characteristic protected by law. Our hiring process includes AI screening for keywords and minimum qualifications, and a virtual recruiter as part of the application process. A human recruiter reviews all results. Click here for details on our virtual recruiter . Everforth CyberCoders will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable state and local law, including but not limited to the Los Angeles County Fair Chance Ordinance, the San Francisco Fair Chance Ordinance, and the California Fair Chance Act. Everforth CyberCoders is committed to working with and providing reasonable accommodation to individuals with physical and mental disabilities. Individuals needing special assistance or an accommodation while seeking employment can contact a member of our Human Resources team at View email address on us.fitly.work to make arrangements.