Senior Silicon Verification Engineer - SystemVerilog & UVM
AMD
A leading semiconductor company is seeking a Design Verification Engineer to join its team in Austin, TX. The successful candidate will be responsible for planning and executing verification of complex digital designs, collaborating with architects and engineers to create comprehensive test plans. Preferred qualifications include experience with System Verilog, verification methodologies, and ASIC development. This role fosters continuous technical innovation and offers attractive benefits in a collaborative work environment. #J-18808-Ljbffr AMD
- ...advanced technology solutions in Austin is seeking a Senior Verification Engineer with over 10 years of experience. The ideal candidate... ...strong expertise in VLSI verification, proficiency in UVM and SystemVerilog, and hands-on experience across multiple verification...SeniorFull time
$150k - $165k
Encore Semi, Inc. is looking for a Sr Design Verification Engineer (Remote) to verify complex digital systems such as ARM-based CPUs.... ...requires ownership of the verification lifecycle using SystemVerilog and UVM. The expected salary ranges from $150,000 to $165,000 annually...SeniorRemote job$136k - $218.5k
NVIDIA, located in Austin, Texas, is seeking an experienced ASIC Verification Engineer. In this role, you will design and maintain verification... ...methodologies. The ideal candidate will have a strong background in UVM and System Verilog, a degree in Engineering, and a passion...Senior$125 - $135 per hour
...leading tech consulting firm is seeking a highly skilled Design Verification Engineer to verify the functionality of GPU designs in Austin, TX. The... ...of experience in the field, proficiency in System Verilog, UVM, and excellent problem-solving skills. This contract position...SeniorContract work- Themesoft Inc. is seeking an experienced verification engineer based in Austin, TX. The ideal candidate will have over 8 years of experience... ...and developing complex verification environments using SystemVerilog. Responsibilities include writing tests and sequences, coordinating...Senior
$156k - $229k
A leading tech company in Austin is looking for a Verification Engineer to contribute to innovative hardware solutions. Responsibilities... ...experience with verification methodologies, including UVM and SystemVerilog. The position offers a base salary of $156,000-$229,000,...Senior- A dynamic tech start-up in Austin is seeking a Senior Verification Engineer to lead RTL design verification efforts. The role requires over... ...of experience in VLSI verification, familiarity with SystemVerilog and UVM methodologies. You'll own the verification process...Senior
$164.47k - $311.89k
...Something Wonderful! Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future.... ...develop and execute functional verification of CPU logic to ensure design... ...Validation methodologies with UVM, System Verilog and industry standard...SeniorLocal areaImmediate startShift work- Arrow Components is hiring a Design Verification Engineer in Austin, Texas. Candidates should have at least 6 years of experience in System Verilog HVL and C/C++. You will be responsible for conducting complete verification cycles, including test plan development, debugging...SeniorRemote work
- Apple’s Silicon Engineering Group seeks a Design Verification Engineer in Austin, TX to verify complex Cellular SoCs for... ...platforms. You will craft reusable UVM testbenches, implement coverage-... ...a Bachelor’s degree with strong SystemVerilog/UVM experience, and hands-on DV expertise...
- ...cutting-edge technology startup is seeking a Sr Mixed Signal Verification Engineer to develop verification strategies for high-speed... ...years of experience in verification, expertise in Verilog/SystemVerilog coding, and proven skills in behavioral modeling. The role...Senior
$192k - $278k
Google is seeking an experienced verification engineer to lead design verification initiatives for CPU developments in Austin, TX. You will ensure quality in our custom silicon solutions, contributing to products that impact millions. The ideal candidate has a minimum of...SeniorFull time- ...focuses on mixed‑signal verification for advanced DSP‑... ...simulate, and debug Verilog/SystemVerilog code for verification... ...analog, and digital engineering teams to validate... ...‑pass success in silicon. Minimum Qualifications... ...Qualifications Experience with UVM (Universal...SeniorFull timeH1b
$136k - $218.5k
...JR2006265 Job Category Engineering Time Type Full time Position Overview Senior ASIC Verification Engineer. Verify our global... ...components using SV/UVM methodology Drive coverage... ...Experience in pre‑silicon verification (UVM, SystemVerilog), ASIC design/implementation...SeniorFull time- ...Role We are looking for a Senior Front End (DV focused) Engineer to join a global team... ...Proficiency in: SystemVerilog / UVM Advanced Testbench architecture... ...SoC architecture, and silicon development flows... ...Knowledge of CDC/RDC, formal verification, and low-power flows...SeniorWork at office
- ...Senior Firmware Verification Engineer Job Description Renesas Electronics America is seeking... ...This role focuses on pre-silicon and post-silicon... ...practical experience with SystemVerilog-based verification. You will... ...Qualifications Experience with UVM or other structured...SeniorWork at officeLocal areaRemote workFlexible hours2 days per week
$190.61k - $269.1k
...candidate to join our ASIC design verification team in a dynamic and... ...analysis. Lead custom SystemVerilog/UVM development, master industry... ...and debug issues in the pre‑silicon environment. Find and implement... ...: Inspire and guide junior engineers, fostering their growth and...SeniorLocal areaImmediate startShift work$195.2k - $325k
...Technologies, Inc. Job Area Engineering Group, Engineering Group >... ...market. Graphics formal verification positions involve developing... ...Support chip bring‑up and post‑silicon debug. Debug functional... ...Verification knowledge - UVM/SystemVerilog preferred. Knowledge of GPU...SeniorWork experience placement$120k - $225k
...hiring experienced Design Verification Engineers to play a key role in developing... ..., emulation, and post-silicon teams to ensure the full system... ...and execution using UVM or other advanced DV methodologies... ...Understanding of Verilog, SystemVerilog, and UVM. ~ Proven track...Senior- ...ultimate goal of enabling human life on Mars. SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in... ...Experience with verification methodologies such as UVM/OVM/VMM Strong object‑oriented programming knowledge Strong...SeniorPermanent employmentWorldwideWeekend work
$163k - $237k
...qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science,... .... 8 years of experience in both Design Verification (UVM/SystemVerilog) and Hardware Emulation. Experience reproducing post-silicon lab failures in emulation or simulation...SeniorWorldwide- Arm Physical IP Inc / Arm Inc. in Austin, TX is seeking a Principal Verification Engineer to develop SystemVerilog/UVM testbenches focusing on Memory Controller verification. This role allows telecommuting up to 3 days a week. The ideal candidate will have a strong background...Remote work3 days per week
$192k - $278k
...Bachelor's degree in Electrical Engineering, Computer Engineering,... ...years of experience with verification methodologies and... ...Verification Methodology (UVM) and SystemVerilog. Experience with processor... ...boundaries, developing custom silicon solutions that power the future...Full timeWorldwide- ...Job Title Senior Verification Engineer Location Austin Role Summary We develop best‑in‑class digital IPs... ...scoreboards, and leverage advanced UVM VIPs Develop directed and constrained... ...coverage models Develop and maintain SystemVerilog assertions (SVA) Apply formal verification...SeniorLocal area
- ...solutions across AI, IoT, and HPC. Responsibilities / Requirements Senior Verification Engineer with 10+ years of experience Strong experience in VLSI verification Proficiency in UVM and SystemVerilog Hands-on experience across at least two full block or system verification...SeniorFull time
- Retym, Inc is seeking a Sr Mixed Signal Verification Engineer in Austin, Texas, to develop cutting-... ...for mixed-signal designs, utilizing UVM methodologies and a collaborative team... ...experience, alongside proficiency in Verilog/SystemVerilog coding and experience in using...Senior
- ...in the U.S. is seeking a Mixed Signal Verification Engineer with over 5 years of experience in behavioral... ...design and proficiency in Verilog/SystemVerilog coding. The role requires familiarity... .... Candidates with experience in UVM and various industry-standard tools are...SeniorVisa sponsorship
$148.3k - $250.7k
A leading semiconductor company is seeking a CPU Silicon Bring up and Validation Engineer in Austin, Texas. In this role, you will support bring up of SoCs using Custom CPUs. Responsibilities include collaborating with design teams to develop test plans, debugging silicon...Senior- Arrow Components is seeking a Post Silicon Engineer for its team based in Austin, Texas. The role focuses on developing and executing validation strategies for our AI/ML hardware products from design through production. Ideal candidates will have 8+ years of experience...Senior
- Intel is seeking a Post Silicon Validation Engineer to join their All Cores Engineering Group in Austin, Texas. In this role, you will validate Intel's leading CPU products, developing and executing validation plans while ensuring high quality standards. The ideal candidate...Senior
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