Remote Senior ASIC Verification Engineer (UVM/SystemVerilog)
$150k - $165kEncore Semi, Inc.
- Remote job
Encore Semi, Inc. is looking for a Sr Design Verification Engineer (Remote) to verify complex digital systems such as ARM-based CPUs. The position requires ownership of the verification lifecycle using SystemVerilog and UVM. The expected salary ranges from $150,000 to $165,000 annually, plus a comprehensive benefits package including health, dental, and vision insurance, 401k options, and tuition reimbursement. #J-18808-Ljbffr Encore Semi, Inc.
- ...California is seeking an experienced engineer to develop and scale test benches using SystemVerilog and UVM methodologies. The role requires expertise in ASIC with a minimum of 8 years in the... ...with a team to ensure verification closure. This position is integral...Senior
$136k - $218.5k
NVIDIA, located in Austin, Texas, is seeking an experienced ASIC Verification Engineer. In this role, you will design and maintain verification... ...methodologies. The ideal candidate will have a strong background in UVM and System Verilog, a degree in Engineering, and a passion...Senior- K2 Space Corporation is seeking a Principal ASIC Design Verification Engineer to verify functionality and performance of custom silicon designs.... ...in ASIC/SoC verification and a solid understanding of SystemVerilog and RTL design. The position is based in Seattle, WA and...Senior
- A technology firm is looking for a Verification Engineer to lead RTL design verification for high-speed digital systems. The ideal candidate... ...developing verification plans and a strong command of SystemVerilog and UVM. They will be responsible for executing test strategies,...Senior
$150k - $165k
Encore Semi, Inc. in Sunnyvale, CA is seeking a Sr Design Verification Engineer to verify complex digital systems, including ARM-based... ...ownership of the full verification lifecycle, utilizing SystemVerilog and UVM to ensure design quality and integrity. The anticipated...Senior- ManpowerGroup, on behalf of our client, is seeking a Verification Engineer 4 in Austin, TX to support ASIC development. You will join the Verification... ...ensure correctness under tight schedules. Strong SystemVerilog/UVM skills and leadership of verification tasks are essential...Senior
$95.5k - $181.7k
...a highly skilled and innovative Senior ASIC/FPGA Verification Engineer to join our Applied Research and... ...environment architecture and design using SystemVerilog with OVM/UVM Creation of written test plans,... ...as on-site, hybrid or remote. The salary range for this role...Remote workSeniorTemporary workWork experience placementWork at officeRelocation packageFlexible hours- A leading engineering talent provider is seeking a Design Verification Engineer for a contract position. The ideal candidate... ..., strong knowledge in SystemVerilog/UVM, and hands-on experience in IP... ...flexible work locations, including remote options. #J-18808-LjbffrRemote workSeniorContract workFlexible hours
- ...Senior ASIC Verification Engineer (AI Hardware) San Jose, California, United States About the Job... ...Verification Engineer (AI Hardware) — Remote (U.S.) — No Visa Sponsorship Overview... ...environments using System Verilog and UVM Create simulation infrastructure,...Remote workSeniorVisa sponsorship
$150k - $165k
Encore Semi, Inc. is seeking a Sr Design Verification Engineer to work remotely in Redmond, WA. This role involves verifying complex digital systems... ...you will manage the verification lifecycle using SystemVerilog and UVM. The anticipated salary ranges from $150,000 to $165...Remote jobSenior- ...Senior Asic Verification Engineer Cornelis Networks is hiring a Senior ASIC Verification Engineer with advanced... ...activities including test-planning, UVM based testbench development,... ...and Systems Location: This is a remote position for employees residing within...Remote workSeniorFull timeFlexible hours
- ...technology company in Chandler, Arizona seeks an experienced ASIC Verification Engineer. The role involves developing verification plans,... ...Candidates must have a strong background in Verilog, VHDL, and SystemVerilog, as well as a degree in Electrical Engineering, with...Senior
$175k - $215k
Waymo is hiring for a verification engineer responsible for building high-performance verification environments for their autonomous vehicle... ...specifications and requires significant expertise in UVM/SystemVerilog and Python. This position follows a hybrid work schedule...- ...advanced technology solutions in Austin is seeking a Senior Verification Engineer with over 10 years of experience. The ideal candidate... ...strong expertise in VLSI verification, proficiency in UVM and SystemVerilog, and hands-on experience across multiple verification...SeniorFull time
- iFlow Inc. is seeking a Design Verification Engineer based in Santa Clara, CA, for a long-term position. The successful candidate will... ...years of experience, showcasing a strong proficiency in SystemVerilog and UVM, alongside debugging skills. Key responsibilities include...Senior
- BLUE ORIGIN is seeking an experienced engineer to lead verification efforts in San Francisco. The role involves... ...verification plans, creating UVM environments, and mentoring junior engineers... ...background in System Verilog and ASIC verification, with 5-8+ years of experience...Senior
- Arrow Electronics in Eden Prairie is seeking a Senior Design Verification Engineer to build scalable verification environments... ...Candidates should have a strong proficiency in SystemVerilog and hands-on experience with UVM. This role requires understanding of constrained...Senior
$136k - $218.5k
NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world... ..., Verilog, System Verilog, UVM, SVA and functional coverage development... ...and ability to work with on-site and remote teams. Proficiency in scripting language...Remote workSeniorWork experience placement- Arrow Components is hiring a Design Verification Engineer in Austin, Texas. Candidates should have at least 6 years of experience in System Verilog... ...and growth opportunities. The position is fully on-site but may consider remote arrangements. #J-18808-Ljbffr Arrow ComponentsRemote workSenior
$178k - $389k
Micron Technology, Inc. in Richardson, Texas is seeking a functional verification engineer with 6-12 years of experience in a UVM/SystemVerilog environment. The role involves full-chip DV planning, testbench development, and formal verification. The ideal candidate will...Senior- ...Origin in Los Angeles is seeking an experienced engineer to lead verification planning for complex systems. The role involves developing UVM environments and ensuring design... ...are met. Candidates should have 5-8 years of ASIC/SoC verification experience and expertise in...
$166k - $249k
...026 Category Engineering Hire Type Employee... ...Range $166000-$249000 Remote Eligible No Date... ...lead in chip design, verification, and IP integration,... ...experienced and highly skilled ASIC Digital Verification... ...testbenches using SystemVerilog and UVM. Collaborating...Remote work- ...Description Job Description Role: ASIC Verification Engineer - ARM Location: Remote Job Type: Contract... ...Verification plans, test case development, UVM environments, Coverage (analysis)... ...and processes, such as UVM / SystemVerilog, Formal verification, Constraint-...Remote workContract work
$136k - $218.5k
...We are now looking for a Senior Verification Engineer for our Memory Management Unit... ...is seeking outstanding ASIC Verification Engineer to verify... ...~ Strong ability with SystemVerilog, C and/or C++, test planning... ...Verification Methodology (UVM), SystemVerilog checkers and...Senior- ...ASIC Verification Engineer Bull is a story. One with a century of European innovation... ..., based on the UVM verification standard, as part... ...coverage models using UVM / SystemVerilog / C++. Track, analyze, and... ...Location Madrid or Barcelona, or remote within Spain Benefits...Remote workSummer workFlexible hours
- A leading semiconductor company is seeking a Design Verification Engineer to join its team in Austin, TX. The successful candidate will be responsible... ...with System Verilog, verification methodologies, and ASIC development. This role fosters continuous technical...Senior
- ...leading tech company in California is seeking an experienced ASIC Verification Engineer to verify designs for their advanced inference... ...years of experience in verification, strong skills in SystemVerilog and UVM, and familiarity with machine learning applications. Benefits...Senior
$76.2k - $187.74k
...ASIC Verification Engineer At Capgemini Engineering, the world... ...The role is 100% remote role About the job... ...test case development, UVM environments, coverage... ..., including UVM/SystemVerilog, formal verification... ...experience and skills, Seniority and performance, Market...Remote workPermanent employmentFull timeContract workLocal area- ...in the United States (WA) seeks an Integrated Circuit Design Verification Engineer to join the Spectacles Team. You will design display ICs for... ...groups to validate complex silicon blocks. The role emphasizes UVM-based verification, assertion-based testbenches, coverage...Senior
$136k - $218.5k
Overview NVIDIA is seeking an outstanding Senior ASIC Verification Engineer to verify the design and... ...in Object Oriented Programming with SystemVerilog Exposure to design and verification... ...like Debussy, GDB), and methodologies (UVM or equivalent) Your work displays a...Senior
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