Senior Verification Engineer: UVM/SystemVerilog for ASICs
Towards AI, Inc.
A tech company in California is seeking an experienced engineer to develop and scale test benches using SystemVerilog and UVM methodologies. The role requires expertise in ASIC with a minimum of 8 years in the field and proficiency in scripting languages like Perl and Python. Responsibilities include regression activities and collaborating with a team to ensure verification closure. This position is integral to the startup environment, emphasizing customer satisfaction and effective progress reporting. #J-18808-Ljbffr Towards AI, Inc.
Vacancy posted 1 day ago
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Sunnyvale, CA1 day ago
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