Senior Design Verification Engineer (eInfochips Inc)

Arrow Electronics Published 28 Mar 2026 Mountain View, CA, USA Full Time Role Highlights Perl Prompt Engineering UVM Regression Startup Electronics Tools, Libraries and Frameworks Mountain View Description The role involves developing and scaling test benches using SystemVerilog and UVM methodologies. Responsibilities include working with AXI, NOC/Crossbar, and performance aspects of designs. The position requires regression, triage, and coverage closure activities. This work is in a start-up mode with limited documentation and requires collaboration with a team to achieve verification closure. Required Qualifications and Skills Candidates require a Bachelor's degree in electrical or computer engineering with a minimum of 8 years of experience in ASIC or a related field. Alternatively, a Master’s Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline is acceptable. The role necessitates verification closure with a team and proficiency in scripting languages such as Make, Perl, and Python. Ensuring customer satisfaction and effectively reporting progress to the customer are also key requirements. #J-18808-Ljbffr Towards AI, Inc.