Verification Engineer

Who we are:

We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.

The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.

Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.

What we need:

An experienced RTL Verification Engineer responsible for ensuring the functionality, correctness, and quality of complex digital designs across ASIC and FPGA platforms. This role focuses on building robust verification environments, executing coverage-driven verification plans, and working closely with RTL design engineers to deliver reliable, high-quality silicon.

The ideal candidate has deep hands‑on experience with SystemVerilog, UVM (or similar methodologies), and modern verification workflows, and is comfortable driving verification efforts from planning through closure.

Key Responsibilities:

• Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies
• Create and execute coverage-driven verification plans aligned with design specifications
• Develop directed and constrained-random test cases and sequences to validate functionality and identify corner cases
• Analyze simulation results, debug complex verification and design issues, and perform root‑cause analysis in collaboration with RTL design engineers
• Implement and track functional and code coverage, driving verification to closure
• Develop reusable verification components and write SystemVerilog Assertions (SVA)
• Participate in design and verification reviews, providing input on design testability, correctness, and optimization
• Automate regression testing and enhance verification infrastructure using Python and scripting
• Contribute to continuous improvement of verification processes, tools, and methodologies

Required Skills and Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 7+ years of experience in digital design verification
• Strong hands‑on experience with UVM‑based or similar verification methodologies
• Proficiency in SystemVerilog, UVM, and Python
• Experience with industry‑standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium)
• Solid understanding of digital design fundamentals
• Experience verifying standard bus and interconnect protocols such as AXI, AXI‑S, and APB
• Experience with high‑speed communication protocols including PCIe, Ethernet (10G/40G/100G), SPI, and I²C
• Strong analytical and problem‑solving skills
• Clear written and verbal communication skills for cross‑functional collaboration
• High attention to detail and ability to deliver reliable, high‑quality verification outcomes
• Ability to work independently and manage tasks to completion

Desired Skills:

• Experience with formal verification techniques and tools
• Experience verifying processor subsystems or SoC‑level designs

Compensation:

Target base salary for this role is $160,000 – $240,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location.