Design For Test (DFT) / DFx Methodology and Architecture Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. HE ROLE: The Circuit Technology team is looking for a passionate and experienced DFT/DFx Methodology, Architecture, and RTL Execution Lead to support high-speed SerDes PHYs , next-generation Memory PHYs , and die-to-die interconnect IPs . In this role, you will own and drive DFT/DFx architecture definition, RTL implementation, methodology development, scan integration support, test constraints, ATPG support, and post-silicon debug for advanced PHY and connectivity IP designs. You will work closely with design, verification, physical design, CAD, product engineering, and test engineering teams to deliver robust, high-coverage, production-ready IP. Be part of a team that delivers industry-leading IP used across AMD SoCs. THE PERSON: The ideal candidate has strong analytical and problem‑solving skills, excellent attention to detail, and the ability to drive complex technical tasks independently. The candidate should be comfortable working hands‑on while also providing technical leadership across architecture, methodology, RTL implementation, verification, and silicon debug. We welcome candidates at multiple experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the level listed in this posting. KEY RESPONSIBILITIES: Define and lead PHY‑specific DFT/DFx architecture and methodology for high‑speed SerDes, Memory PHY, and die‑to‑die interconnect IPs. Implement DFT/DFx features in RTL using Verilog/SystemVerilog. Develop and support DFT micro‑architecture, including scan architecture, test modes, clocking, reset, isolation, bypass, and observability features. Support JTAG/IJTAG, ICL/PDL, scan compression, at‑speed scan, and hierarchical DFT implementation. Support Siemens Tessent‑based or equivalent industry‑standard DFT flows for ATPG, pattern generation, pattern validation, and debug. Support scan stitching, scan readiness checks, test coverage analysis, and DFT rule/debug closure. Develop and maintain DFT timing constraints, test‑mode constraints, and integration guidelines compatible with front‑end and physical design flows. Perform gate‑level simulation and debug using tools such as Synopsys VCS and Verdi. Drive SpyGlass or equivalent lint/DFT‑readiness analysis to identify scan, controllability, observability, and test coverage gaps. Plan, implement, and verify MBIST‑related features for embedded memories. Support ATPG pattern generation, simulation, debug, and delivery to test engineering. Partner with Test Engineering and Product Engineering on silicon bring‑up, tester pattern debug, diagnosis, and yield‑learning activities. Develop efficient, reusable DFx flows, scripts, checkers, and methodologies for IP‑level and SoC‑level integration. PREFERRED EXPERIENCE: Hands‑on experience with Siemens Tessent DFT flows, such as Tessent Shell, Tessent Scan, Tessent ATPG, Tessent TestKompress, Tessent MemoryBIST, IJTAG, ICL/PDL, and/or Streaming Scan Network/SSN. Relevant industry experience in DFT, DFx, RTL design, semiconductor IP development, or SoC test methodology. Level will be determined based on experience and interview assessment. Strong understanding of DFT architectures and micro‑architectures, including scan, compression, test clocks, test resets, lock‑up latches, clock gates, scan anchors, and test access mechanisms. Hands‑on RTL coding experience in Verilog and/or SystemVerilog. Experience with industry‑standard ATPG, scan insertion, and DFT implementation tools. Familiarity with JTAG, IJTAG, ICL/PDL, scan compression, at‑speed scan, and hierarchical DFT concepts. Experience with gate‑level simulation, debug, and waveform analysis using tools such as Synopsys VCS and Verdi. Experience analyzing DFT‑readiness, lint, controllability, observability, and test coverage issues. Understanding of MBIST planning, implementation, verification, and debug. Understanding of low‑power design concepts such as power gating, multi‑voltage domains, multi‑Vt usage, isolation, retention, and voltage scaling. Good understanding of high‑performance and low‑power digital design fundamentals. Knowledge of common fault models, including stuck‑at, transition, path delay, gate‑exhaustive, IDDQ, and cell‑aware fault models. Strong debug and problem‑solving skills across RTL, gate‑level netlists, constraints, patterns, and silicon behavior. Experience developing or supporting hierarchical DFT flows for complex SoCs or reusable IPs. Experience with pattern retargeting, pattern validation, tester bring‑up, and production pattern debug. Experience with post‑silicon diagnosis, failure analysis, yield learning, and tester‑based debug. Experience with fault campaigns, safety‑oriented test methodology, or functional safety flows. Scripting experience in Tcl, Python, Perl, shell, or similar languages for flow automation and debug. Experience working on high‑speed PHYs, SerDes, Memory PHYs, die‑to‑die interconnects, or other mixed‑signal‑adjacent digital IPs. Familiarity with physical‑design impacts of DFT, including scan routing, test clocking, timing closure, congestion, and low‑power test constraints. Strong communication skills and ability to work across design, verification, CAD, physical design, and test engineering teams. ACADEMIC CREDENTIALS: Bachelor’s, Master’s or PhD degree in Electrical Engineering, Computer Engineering, Computer Science or related field. LOCATION: Santa Clara, CA or Austin, TX This role is not eligible for visa sponsorship. EEO STATEMENT AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available. This posting is for an existing vacancy. #J-18808-Ljbffr