Lead ASIC Design Engineer - High-Performance Networking
Hewlett Packard Enterprise Development LP
Hewlett Packard Enterprise Development LP in Sunnyvale, CA, seeks a Principal ASIC Design Engineer to architect high-performance networking chip modules. You will specify, implement, and verify RTL in Verilog/SystemVerilog, craft coverage plans, and drive power-conscious designs. Lead cross-functional teams with a focus on timing closure and quality. The role requires 15+ years of experience, a strong background in ASIC design, and excellent communication. #J-18808-Ljbffr Hewlett Packard Enterprise Development LP
Vacancy posted 1 day ago
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