Senior architecture architect

About The Role The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next‑generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.
Senior SoC Chiplet Architect We are seeking a Senior SoC Chiplet Architect to define and lead the architecture strategy for multi‑generation, chiplet‑based SoC platforms targeting next‑generation data center workloads. This role is responsible for chiplet partitioning, die‑to‑die (D2D) interconnect architecture, and system‑level trade‑off analysis across performance, power, area (PPA), cost/yield, and software complexity.
Responsibilities Chiplet Architecture Strategy and Roadmap Define the monolithic vs. Lead architecture studies for 2‑die, 3‑die, and multi‑chiplet scaling (compute + I/O/network + memory/accelerators), including partition boundaries, SKU scalability, and future‑proof modular upgrades.
Produce executive‑ready architecture options and recommendations for leadership decisions.
Chiplet Partition, Resource Scaling, and System Topology Drive functional partitioning across chiplets (compute, networking/I/O, accelerators, memory controllers, security/management), balancing PPA, D2D bandwidth/latency, validation complexity, and product flexibility.
memory channels, PCIe lanes, pipeline scaling) and how these scale with chiplet count and topology.
Specify any required logic/gaskets and integration constraints to enable modular assembly and consistent SW‑visible behavior.
Die‑to‑Die (D2D) Interconnect Architecture and QoS Architect D2D communication for high bandwidth, low latency, and reliability across chiplets; arbitration, prioritization, isolation) and ensure the architecture supports workload‑driven traffic patterns at scale.
Align D2D choices with industry standardization direction and ensure project‑specific needs can be encapsulated cleanly.
Architect clocking and reset distribution (reference clock delivery, local PLL strategies, reset sequencing, debug/manufacturing hooks) and ensure robust bring‑up across all dies.
Drive the chiplet‑aware boot and early firmware architecture (e.g., parallel boot considerations, coordinated reset control) in partnership with FW/platform teams.
RAS, Debug, and Observability Across Chiplets Define cross‑chiplet error reporting, containment, and recovery policies, including consistent crashdump, telemetry access, and actionable observability for post‑silicon debug.
Specify debug/trace infrastructure assumptions to ensure chiplet partitioning does not compromise lab efficiency or field diagnosability.
Quantitative Trade‑Off Studies Lead quantitative trade studies across performance, power, area, cost/yield, and schedule; identify bottlenecks and propose architecture‑level mitigations.
Cross‑Functional Technical Leadership Drive alignment across architecture, RTL, DV, FW/SW, packaging, and platform teams; Defines long‑term chiplet architecture direction across product lines.
Evaluates multidimensional tradeoffs (PPA, cost, schedule, risk).
Understands full‑stack implications (hardware, firmware, software, manufacturing).
Translates complex architecture into clear recommendations.
Partners effectively across architecture, packaging, and platform teams.
Qualifications Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM‑related field.
7+ years of experience in SoC/system architecture, including end‑to‑end architecture definition from requirements to silicon execution.
Run architecture trade‑off studies and communicate decisions crisply to senior technical and business stakeholders.
Hands‑on experience with system bring‑up flows and architecture‑driven debug/telemetry planning across complex SoCs.
Architecture fundamentals in interconnects/fabrics, memory subsystem behavior, performance modeling, and PPA tradeoffs.
Experience building or consuming cost/yield models for architectural decision‑making (including explicitly scoping which cost elements are included).
EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, sexual orientation, gender identity, gender expression, or any other characteristic protected by federal, state, or local law.

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