Physical Design Engineer

Job Title: Physical Design Engineer

Location: Santa Clara, CA

If you want to know about the requirements for this role, read on for all the relevant information.

THE ROLE:

This is a Physical Design Engineering role that will require to take the design from RTL to GDS with synthesis, Place n Route, timing, and Physical Verification.

RESPONSIBILTIES:

This engineer will work on high-speed multi-gigabit SerDes PHY designs. This includes automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications, automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. You will also support floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

PREFERRED SKILLED SETS:

• 2-5+ years working experience, preferably with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs
• Proficiency in Python and/or Perl is required. Additional languages are a plus.
• Versatility with scripts to automate design flow, and quality checks.
• Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications.
• Experience in automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
• Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applications
• Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery. xhqgsiq
• Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation

EDUCATION:

• Major in EE, CS or related, master’s degree preferably with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs.