Analog Layout Engineer
Saksoft
Job Title: Analog Layout Engineer Location: Cupertino, CA (on-site) Hire Type: Contract Duration: Long-term Job Description Minimum 6+ years of experience in Analog layout design. Experience developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level. Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys. Experience with layout of high-performance high-speed analog mixed-signal blocks such Transceivers, CMOS drivers, high-speed Data converters and PLLs. Experience with floor planning, block level routing and top-level chip assemble. Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration. #J-18808-Ljbffr Saksoft
Vacancy posted 1 day ago
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