DFT Engineer

Job Description Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be working on DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production. The candidate would be required to work on various phases of SoC DFT related activities for APD's designs – DFT Architecture, test insertion and verification, pattern generation, coverage improvement, post silicon debug, and yield improvement to meet the product test metrics. The role involves working with the Physical Design and STA team for DFT mode timing closure and could also involve direct interaction with external customers. Responsibilities Understand Broadcom and customer DFT feature requirements, and DPPM goals and define appropriate DFT specifications for the ASIC. Implement DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration. Generate, verify, and debug test vectors before tape release and on ATE during silicon bring up. Assist with silicon failure analysis, diagnostics, and yield improvement efforts. Interface with the customer, physical design and test engineering/manufacturing teams located globally. Collaborate with I/P DFT engineers and other stakeholders. Debug customer returned parts on the ATE. Innovate newer DFT solutions to solve testability problems in 3nm and beyond. Automate DFT and test vector generation flows. Skills/Experience Bachelor's and 8+ years of related experience; or Master's degree and 6+ years of related experience. Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others). Experience with Scan Insertion and scan compression (DFT Compiler, Mentor TestKompress, etc.). Experience with Logic BIST design and debugging. Well-versed in ATPG vector generation, simulation, and debugging (TetraMax, Fastscan). Experience in Verilog coding, testbench generation and simulation. Memory BIST insertion and verification experience on embedded SRAM, CAM, eDRAM, ROM. Knowledge in boundary scan verification, IEEE1149.1 and IEEE1149.6. Basic knowledge of Test-STA and constraints. Strong background on IEE1687, IJTAG, ICL, and PDL. Ability to work in a multi-disciplined, cross‑department environment. Solid knowledge of analog and digital circuit design, and device physics fundamentals. Understanding of Si processing, logical and physical synthesis, and transistor reliability principles. Excellent problem‑solving, debugging, root cause analysis, and communication skills. Understanding of statistical process control and data analysis techniques to drive silicon yield improvements and quality metrics. Project management capabilities to track and prioritize competing deliverables across cross‑functional stakeholders including Test Engineering, Reliability, and Operations. Experience working on ATE is a plus. Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification, and silicon debug is a plus. Experience working on Tessent SSN is a plus. Compensation and Benefits The annual base salary range for this position is $120,000 - $192,000. Eligible for a discretionary annual bonus and a new hire equity grant, plus annual equity awards. Broadcom offers a competitive benefits package including medical, dental, vision plans, 401(k) with company match, Employee Stock Purchase Program, Employee Assistance Program, company paid holidays, paid sick leave, vacation time, and Paid Family Leave and other applicable leaves of absence. #J-18808-Ljbffr Broadcom