SoC Power Lead, Memory Subsystem
$192k - $278kLead the definition of power requirements for Tensor mobile System-on-Chips (SoCs) to achieve Power-Performance-Area (PPA) with a primary focus on the memory subsystem (memory controller, DDRPHY, DRAM).Own and drive cross-functional teams to deliver on power Key Performance Indicators (KPIs) for the memory subsystem and other major SoC IPs.Propose and drive power optimizations for the memory subsystem throughout the design process from concept to mass productization.Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.Represent status of SoC power to the executive leadership team.Minimum qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.10 years of experience with memory subsystem architectures, including for mobile SoCs.Experience in power management or low power design/methodology, as well as with low power architecture and power optimization techniques.Experience with full product delivery cycle (e.g., definition, architecture, design and implementation, testing, productization).Preferred qualifications:Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.Experience with memory subsystem architectures, cache hierarchies, system-level power and performance modeling, SoC-wide traffic analysis and optimizations, LPDDR standards, etc.Excellent leadership, organizational, and communication skills.Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $278000 (USD) + 20% bonus target + equity + benefitsLearn more about benefits at Google.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.10 years of experience with memory subsystem architectures, including for mobile SoCs.Experience in power management or low power design/methodology, as well as with low power architecture and power optimization techniques.Experience with full product delivery cycle (e.g., definition, architecture, design and implementation, testing, productization).
$200k - $250k
...experienced and highly motivated Lead SoC Architect to lead the... ...development, performance modeling, subsystem integration, and cross-... ...tradeoff analysis for performance, power, area, bandwidth, latency,... ...modeling environments. Define memory hierarchy, NoC/interconnect...SuggestedWork at officeLocal areaNight shift$240k - $333k
Define the SoC limits management by integrating hardware triggers... ...to protect silicon health.Lead cross-functional teams to standardize... ...features, including Power Telemetry, Estimators, and Droop... ...holistic "Limits Management" subsystem. Your work ensures our SoCs deliver...SuggestedWorldwide- ...Apple Inc. in Cupertino seeks a SoC DRAM Memory Subsystem Validation Engineering Program Manager to lead memory readiness for our custom SoCs. You will drive bring-up, validation and complex debug across multi-functional teams, shaping the DRAM roadmap and coordinating...Suggested
- ...We are looking for a senior SoC Chip Lead to join our San Jose office.... ...level tradeoffs across compute, memory bandwidth, and on-chip... ...debug spanning floor-planning, power distribution, clocking, timing... ...System Interconnects, Processor subsystems, and 2.5D/3D packaging and chiplet...SuggestedWork experience placementWork at officeWorldwide
- ...leader to verify and deliver its next generation Physical AI SoC. You will work with architects, RTL engineers, software... ...through sign-off and tape-out, covering boot, root of trust, clock/reset topology, low-power behavior, and IO/memory subsystems. #J-18808-Ljbffr VelauraSuggested
$237.5k - $286k
...Principal PCIe Subsystem RTL lead TylSemi, Inc. San Jose, California, United States About this... ...hundreds of chips, deliver clean power at scale, and move terabits of data without... ...lead for next generation chiplet based SoCs for High-performance Compute and AI silicon...Remote workShift work$272.9k - $409.3k
...Engineering Group, Engineering Group SoC Architecture General Summary As a SoC... ...Architect, you will create performance and power models for the fabric NoC / DRAM controller... ...interconnect NoCs, distributed system caches, memory controllers, IO controllers Verify...Work experience placementWork from homeNight shift$397.8k
...are seeking an experienced SoC Interconnect Technology Team Lead to drive the architecture,... ...focus on performance, power efficiency, and system-level... ...Collaborate with CPU, GPU, NPU, memory, and system teams to... ...architecture across multiple subsystems.Passion for building...Work at officeLocal areaNight shift- Google is seeking a Senior Staff CPU Cache Subsystem Design Engineer to lead front-end design teams, define... ...generation CPU subsystems across target SOCs. You will collaborate with architecture, software, verification, power, DFT, and physical design teams to optimize...
- Velaura is seeking an experienced RTL Lead to drive the implementation of our next-generation Physical AI SoC. The role blends architectural influence with hands-... ...methodologies, and oversee RTL across compute engines, memory subsystems, interconnects, and system infrastructure #J...
- AMD in Santa Clara, CA is seeking a Memory Sub-system Validation Lead to drive pre- and post-silicon validation of on-die HBM for the Datacenter GPU line. You will partner with DRAM, Memory Controller, DV, DDR PHY, DRAM product engineering and software teams to ensure memory...
- Google's Silicon Development team is seeking a Technical Program Manager III to lead memory-related silicon programs across concept, architecture, design, validation and NPI, coordinating with SoC teams and external vendors. You will plan requirements with internal...
- SiFive is seeking a Principal Design Verification Engineer to spearhead CPU-subsystem power-management verification across complex SoC environments, delivering data-center-grade signoff readiness. You will define architecture-aware verification strategies, drive cross-...
- Rivian in Palo Alto, CA is seeking a highly skilled Power Integrity & Power Architecture Engineer to lead end-to-end design, modeling, simulation, and post-silicon validation of advanced SoC power delivery architectures. You will bridge SoC design, power architecture,...
- Bolt Graphics, Inc. is seeking a Lead SoC Architect to define the technical direction for next-generation semiconductor products in Sunnyvale... ...experience in SoC architecture and a strong understanding of subsystem integration. This role focuses on defining scalable...Local area
- Intel Corporation in Santa Clara, CA is seeking a Data Center SoC Power Architect to shape the power, performance, and efficiency strategy for world-class compute platforms powering cloud, AI, and HPC workloads. You will collaborate across silicon, firmware, software, and...
$100k
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance... ...Engineer to lead post-silicon power characterization and correlation activities... ....What you will learnHow state-of-the-art SoCs behave in real silicon across diverse workloads...Permanent employment$232k - $368k
NVIDIA is seeking an outstanding SoC Verification Engineer to serve as a Person-in-Charge... ...SoC designs in the world. These chips power data center AI infrastructure, AI client computing... ...leadership with clear mitigation plans.Lead risk identification and mitigation...Full time$200k - $300k
...Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a member of the CPU-specific... ...for the product. THE ROLE As a Custom Library and Memory Layout Lead, you will participate in the following : Lead physical layout...For contractors$200k - $300k
...seeking an experienced RTL Lead to help drive the... ...generation Physical AI SoC. This role combines architectural... ...across AI workloads, memory systems,runtime... ...compute engines, memory subsystems,interconnect, control logic... ...Develop high-quality, power-efficient, and scalable...Flexible hours- ...looking for a CAD Back-end Lead to build, integrate,... ..., timing and power analysis, physical verification... ...block-level, hierarchical, subsystem-level, and full-chip... ...standard-cell libraries, memories, IP collateral, RC... ...multiple successful ASIC or SoC programs. Experience...
- ...seeking an analytical and strategic SoC Design Verification (DV) Lead to architect, drive, and execute the... ...silicon through rigorous block-level, subsystem, and full-chip verification. What... ...of critical system features like power management (UPF), clocking/resets, and...Remote workShift work
- ...are determined to help solve them.AMD is powering the next generation of supercomputing, high... ...the world forward.THE ROLE:We are seeking a lead PPA Architect to ensure that CPU Core &... ...reviews across the product definition stack: SoC architecture, physical design...Temporary work
$200k - $275k
...Accelerator Architect Lead Boston, MA; San Jose, CA... ...characterized by ultra-low power consumption and deep... ..., analog and digital subsystems, firmware, and system interfaces... ...processors, firmware, memory subsystems, and AI... ...multiple projects and SoC generations. Minimum...Permanent employmentFull timeWork at officeDay shift- 1st Avenue Power seeks a Technical Program Manager for Power Systems to drive delivery of PCS, inverters, and DC-DC converters for utility-scale solar and storage. You will manage schedule, budget, scope, and risk across hardware, firmware, and test teams. You will coordinate...
$220k - $250k
...than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-... ...inference.We are seeking an experienced System Signal Integrity and Power Integrity Engineer Lead to solve complex, high‑impact integrity...Flexible hours- Google is seeking a Global Supply Chain and Sourcing Manager for Devices and Services to lead Memory supplier strategy and procurement. You will align with Product Management, Hardware/Software Engineering, and Operations to ensure optimal supply and quality while building...
- DensityAI, Inc. seeks a senior verification engineer to own block- and SOC-level formal verification for our AI accelerator silicon,... ...through scale-out. You will use and develop AI-assisted tool flows and lead proof strategies, working closely with RTL designers to drive...Visa sponsorship
- Google LLC in Mountain View, CA is seeking a Share TPU Design Verification Engineering Lead to drive IP/SoC functional verification across cross‑functional teams. The role emphasizes leadership, architecture collaboration, and defining verification strategies for multiple...
- AMD is seeking a Lead Physical Design Engineer in Santa Clara, CA to ensure CPU Cores and SOC meet thermal and silicon performance targets. The role focuses on physical design methodology and power/thermal constraints across IPs, driving cross-functional alignment and...
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