Sign up to access all features of our service.
  • Job search
  • Favorites
  • Create a CV
    New
  • Salaries
  • Subscriptions

Senior Design Verification Engineer

Auradine

Design Verification Engineer

We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next-generation Physical AI SoC. In this role, you will work closely with architects, RTL engineers, software engineers, and system teams to verify complex hardware blocks and system-level behavior across the entire platform. You will help establish confidence in the correctness, performance, reliability, and safety of the architecture—from individual RTL blocks to complete HW/SW systems running real-world workloads. We welcome engineers at all experience levels who enjoy understanding systems, finding corner cases, and solving challenging technical problems.

Responsibilities

Develop and execute verification strategies for key portions of the Velaura SoC.

Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, and related methodologies.

Collaborate with architects and RTL engineers to define verification plans, coverage goals, and correctness criteria.

Verify compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other critical SoC infrastructure.

Perform HW/SW co-verification involving firmware, drivers, runtime software, and operating system interactions.

Verify performance, latency, bandwidth, QoS, and real-time system behavior under representative workloads.

Develop assertions, checkers, scoreboards, and automated verification infrastructure.

Participate in emulation, FPGA prototyping, and pre-silicon software bring-up activities.

Drive bug investigation, root-cause analysis, and debug across hardware and software boundaries.

Post-silicon debug and root cause analysis.

Leverage modern engineering tools, including AI-assisted verification workflows, to improve productivity, quality, and coverage.

Contribute to a culture of technical excellence and continuous improvement.

Required Qualifications

10+ years of experience verifying complex digital systems.

Strong analytical and problem-solving skills. Strong understanding of computer architecture, microarchitecture, SoC architecture and digital design fundamentals. Experience in understanding low power methodologies and verification criteria. Strong understanding of CDC issues, clocking and reset verification. Experience with SystemVerilog, UVM, C/C++, assertions, coverage-driven verification, and related methodologies. Familiarity with formal verification techniques and tools. Experience with emulation, FPGA prototyping, or pre-silicon validation environments. Understanding of memory systems, interconnect fabrics, caches, DMA engines, processors, or accelerator architectures. Experience debugging complex system-level issues. Ability to work effectively in a collaborative, multidisciplinary engineering environment.

Preferred Qualifications

Experience with one or more of the following standards: ISO 26262, IEC 61508, IEC 61511, ISO 13849 Experience with AI, machine learning, or edge AI hardware. Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems. Experience verifying QoS, latency-sensitive, or real-time systems. Experience with HW/SW co-verification and system-level validation. Exposure to performance modeling, profiling, and workload characterization. Experience using modern AI tools and workflows to accelerate engineering productivity. Background in CPUs, GPUs, AI accelerators, networking and communications silicon, storage and data movement architectures, robotics and autonomous systems, automotive and ADAS platforms, aerospace and defense systems, real-time and safety-critical computing, or functional safety architectures and methodologies.

Why Velaura?

Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world. This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: View email address on click.appcast.io. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.

Vacancy posted 3 days ago
Similar jobs that could be interesting for youBased on the Senior Design Verification Engineer in Santa Clara, CA vacancy
  •  ...subsystem and standard interfaces using SystemVerilog/UVM. Develop verification plans, UVM testbenches, test cases, assertions (SVA), and...  ...management, and exception handling. Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.... 
    Senior

    ACL Digital

    San Jose, CA
    20 hours ago
  • $136k - $218.5k

    We're now looking for a Senior Digital Design Verification Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel... 
    Senior
    Full time

    Nvidia

    Santa Clara, CA
    4 days ago
  • $136k - $218.5k

    NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position offers you an outstanding opportunity to influence performance of the next generation GPU and SoC, allowing you to... 
    Senior
    Full time
    Work experience placement
    Remote work

    Nvidia

    Santa Clara, CA
    3 days ago
  • $164.47k - $269.1k

    Job Details:Job Description: About the RoleAs a Senior SoC Design Verification Engineer, you will lead verification efforts for complex system-on-chip (SoC) designs that enable Intel's next generation of client computing and AI technologies. You will drive verification... 
    Senior
    Full time
    Local area
    Immediate start
    Worldwide
    Shift work

    Intel

    Santa Clara, CA
    4 days ago
  • $164.47k - $311.89k

    Job Details:Job Description: About the RoleIntel is seeking a Senior Design Verification Engineer for the Silicon Chassis team. In this role, you will own end-to-end verification of critical chassis and interconnect IP blocks from planning through signoff. You will drive... 
    Senior
    Full time
    Internship
    Local area
    Immediate start
    Shift work

    Intel

    Santa Clara, CA
    4 days ago
  • $167.7k - $245.2k

     ...help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able...  ..., experiment more, and work quickly. As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary... 
    Senior
    Full time
    Temporary work
    Local area
    Flexible hours

    CISCO Systems

    San Jose, CA
    2 days ago
  •  ...possibilities of AI. Location:Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week.The role:Senior Staff Design Verification Engineer What you will do:We want to build a company and a culture that sustains the tests of time. We offer the candidate... 
    Senior
    3 days per week

    d-Matrix

    Santa Clara, CA
    4 days ago
  •  ...Design Verification Engineer Immediate need for a talented Design Verification Engineer. This is a fulltime opportunity with long-term potential and is located in San Francisco, CA (Onsite). Key Requirements and Technology Experience: ~6+ years of experience with... 
    Senior
    Full time
    Immediate start

    Pyramid Corporation

    San Jose, CA
    1 day ago
  • $142.6k - $206.5k

     ...development, which includes participating in high-level product specifications, logic/RTL design and implementation, RTL verification, IP FPGA validation and debugging. As Lead DV Engineer focusing on IP Verification & Validation, you will be responsible for carrying out... 
    Senior
    Local area
    Shift work

    Altera

    San Jose, CA
    3 days ago
  • $134.39k - $201.3k

     ...principle — sharing reusable components, verification environments, and knowledge across all...  ...silicon.As part of the COE, you will design, verify, and deliver IP subsystem building...  ...’s or master’s degree in electrical engineering, Computer Engineering, or related field... 
    Senior
    Permanent employment
    Full time
    Internship
    Work from home
    Shift work

    Marvell

    Santa Clara, CA
    3 days ago
  • $153.5k - $310.5k

     ...Senior Design Verification Engineer This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live... 
    Senior
    Work experience placement
    Work at office
    Local area
    Immediate start
    2 days per week

    HPE

    Sunnyvale, CA
    1 day ago
  •  ...millions of patients worldwide.We’re a team of engineers, clinicians, and innovators united by...  ...from test-planning to closing verification using coverage metricsHands-on testbench development UVMWork closely with the design team to review specifications and architecture... 
    Senior
    Local area
    Worldwide
    Flexible hours

    Intuitive Surgical

    Sunnyvale, CA
    4 days ago
  •  ...Experience with Verilog, System Verilog, and modern verification libraries like UVM 10+ years of ASIC design verification experience Experience / Background...  ...TCL is a plus Collaborate with architects, hardware engineers, and firmware engineers to understand the new... 
    Senior

    Infobahn Softworld Inc

    Santa Clara, CA
    2 days ago
  • $145k - $234.5k

    Senior ASIC Design Verification Engineer (Hardware) Senior ASIC Design Verification Engineer (Hardware) Direct message the job poster from Palo Alto Networks At Palo Alto Networks everything starts and ends with our mission: Being the cybersecurity partner of choice,... 
    Senior
    Full time
    Casual work
    Work at office

    Palo Alto Networks

    Santa Clara, CA
    4 days ago
  • Abbott in Santa Clara, CA seeks a Senior Product Development Engineer to lead design verification activities for medical device systems. You will develop test methods, write protocols, investigate performance issues, and drive corrective actions in a fast-paced R&D environment... 
    Senior

    Abbott

    Santa Clara, CA
    3 days ago
  • $163k - $236k

    Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.Create and enhance constrained-random verification environments using SystemVerilog and UVM... 
    Senior
    Worldwide

    Google

    Sunnyvale, CA
    4 days ago
  • $163k - $236k

    Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.Create and enhance constrained-random verification environments using SystemVerilog and UVM... 
    Senior
    Worldwide

    Google

    Sunnyvale, CA
    14 hours ago
  • $163k - $237k

    Lead CAD methodology engineers to provide support for chip Design Verification (DV) teams, and manage and mitigate support issues for tool flows.Partner with chip...  ...its integration within AI/ML-driven systems. As a Senior Engineer within Google's silicon team, you will... 
    Senior
    Worldwide

    Google

    Sunnyvale, CA
    20 hours ago
  • $163k - $237k

    Develop verification plans and test plans for digital intellectual properties (IPs) and subsystems...  ...:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science...  ...and subsystems.Experience working with design verification (DV) testbenches or... 
    Senior
    Worldwide

    Google

    Mountain View, CA
    2 days ago
  •  ...diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a Senior CPU Design Verification Engineer, you will join a CPU testbench infrastructure team responsible for building scalable verification environments for... 
    Senior

    AMD

    Santa Clara, CA
    1 day ago
  • $163k - $237k

    Verify designs using verification techniques and methodologies.Work cross-functionally to debug failures and verify the functional correctness...  ....Minimum qualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field,... 
    Senior
    Worldwide

    Google

    Mountain View, CA
    2 days ago
  • $163k - $236k

    Lead comprehensive verification strategies and signoff for complex blocks where the source is...  ...quality from HLS code to generated RTL.Design and maintain advanced environments, including...  ...for verifiability and mentor junior engineers on the nuances of HLS verification.Minimum... 
    Senior
    Worldwide

    Google

    Mountain View, CA
    20 hours ago
  • $168k - $264.5k

     ...forefront of technological advancement.As a member of our Mixed Signal Design Validation team, you will be responsible for the bring-up and...  ...and chip bring-up activitiesTake ownership for training new engineers in validation practicesWhat we need to see:A BS degree or... 
    Senior
    Full time

    Nvidia

    Santa Clara, CA
    4 days ago
  •  ...enterprise environments, including Goldman Sachs, IBM Cloud, Microsoft Azure, and Oracle.THE PERSON:We are seeking a high‑impact Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, high‑performance ASIC... 
    Senior

    AMD

    Santa Clara, CA
    4 days ago
  • $119.8k - $234.7k

     ...Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft...  ...organization within SCHIE is responsible for design, development, manufacturing and...  .... We are looking for a Senior Silicon Design Verification Engineer to join the team.#SCHIE #CSMEResponsibilitiesThe... 
    Senior
    Ongoing contract
    Permanent employment
    Work at office
    Local area
    Worldwide
    3 days per week

    Microsoft

    Mountain View, CA
    4 days ago
  • $119.8k - $234.7k

     ...Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s...  ...AI Silicon Engineering (AISiE) SoC Design Verification team is instrumental in defining and...  ...infrastructure. We are looking for a Senior Design Verification Engineer to join the... 
    Senior
    Ongoing contract
    Permanent employment
    Work at office
    Local area
    Worldwide
    3 days per week

    Microsoft

    Mountain View, CA
    4 days ago
  • $165k - $241.4k

     ...Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography...  ...smaller ASIC team can provide.Your Impact Participate in the ASIC design verification for Cisco high-end switching products.Architect, develop,... 
    Senior
    Full time
    Temporary work
    Local area
    Flexible hours

    CISCO Systems

    San Jose, CA
    20 hours ago
  • $250k - $300k

     ...ultra high-speed inference.Key ResponsibilitiesWork with architects, designers, post silicon and software engineers to ensure a high-quality design that works first silicon.Develop and implement verification strategies, detailed tests and coverage plans based on micro-... 
    Senior

    Cerebras Systems

    Sunnyvale, CA
    4 days ago
  • $120k - $225k

     ...Design Verification Engineer We're hiring experienced Design Verification Engineers to play a key role in developing and verifying the designs that will bring our next-generation AI processors to life. Mythic is building the future of AI computing with breakthrough... 
    Senior

    Mythic

    Palo Alto, CA
    3 days ago
  • $183k - $247.6k

     ...customers across all industries. We are seeking experienced Design Verification Engineers to build the next generation of our cloud server chips....  ...environment that celebrates knowledge sharing and mentorship. Our senior members enjoy one-on-one mentoring. We care about your... 
    Senior
    Local area
    Work from home
    Flexible hours

    Amazon

    Cupertino, CA
    20 hours ago

Do you want to receive more vacancies?

Subscribe and receive similar vacancies to Senior Design Verification Engineer. Be the first to apply!