Principal Design Engineer

Overview Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Principal Design Engineer in Micron’s NVEG organization will lead the development, layout, and optimization of breakthrough datapath circuits for next‑generation NAND flash memory, acting as a key technical leader driving task forces and making strategic architectural decisions to achieve critical design targets such as unprecedented data rates and lower power consumption. Responsibilities Manage, design, and verify major IO/datapath blocks (input receivers, serializers, deserializers, clock distribution, equalizers, ZQ calibration, ONFI training features, and wave pipelines) to meet performance specifications. Model layout parasitics and optimize signal quality, conduct regular layout reviews, and pursue area reduction and power efficiency opportunities. Collaborate with project integration and other functional design teams to define and negotiate specifications for major block interfaces. Partner with Product Engineering to define silicon experiments, drive silicon debugging, and propose architectural fixes to improve yield and performance. Liaise with Applications Engineering to evaluate feasibility of new specifications, balancing customer needs against design constraints. Document methodologies clearly and present final results to expert panels and team members. Mentor engineers newer to the field, enhancing the team's technical skills. Minimum Qualifications BS or MS in Electrical Engineering or related field with 8+ years of IC design experience. 10+ years of in‑depth knowledge and deep intuitive understanding of high‑speed IO circuit performance, power/area optimization, and top‑level chip architecture/floorplanning. Proven track record in physical design flows, layout optimization, and parasitic extraction. Demonstrated experience with high‑speed interfaces for NAND and sophisticated training/calibration features. Strong project management skills with the ability to lead sophisticated design initiatives and communicate progress and outcomes to diverse teams. Preferred Qualifications Hands‑on experience applying AI to improve design quality, workflow efficiency, or layout optimization. Experience with DRAM interfaces (DDR4/5, LPDDR5/6, HBM3/3E/4) or other high‑speed industry standard interfaces. Experience with signal/power integrity (SI/PI) and chip‑level power delivery network (PDN) design and optimization. Comprehensive understanding of sophisticated CMOS device physics, device reliability mechanisms, BSIM modeling, and CMOS targets for high‑speed IO operation. Salary The U.S. base salary range for this full‑time position is $176,000.00 – $298,000.00 per year, with additional compensation potential through benefits, bonuses, and equity. Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws. #J-18808-Ljbffr