SoC Physical Design Engineer, STA/Timing
$147.4k - $272.1kApple
SoC Physical Design Engineer, STA/Timing Join us to help deliver the next groundbreaking Apple product. In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology. Description Work with design teams to understand and debug constraints and facilitate logic changes to improve timing. Work with the Physical Design team, highlighting issues and best practices. Help create timing ECO’s for project tapeout. Create and maintain scripts and methodologies for analysis and runs. Create documentation and help with guidelines/specs. Deep analysis of timing paths to identify key issues. Implement timing infrastructure. Minimum Qualifications Minimum BS and 3+ years of relevant industry experience. Experience with large design STA and Timing Closure. Programming skills with Perl and TCL. Preferred Qualifications Hands‑on experience in STA. Familiar with important aspects of timing of large high‑performance SoC designs in sub‑micron technologies. Proficient in STA and methodologies for timing closure and have a fundamental understanding of noise, crosstalk, and OCV effects, among others. Familiar with circuit modeling, including SPICE models, and worst‑case corner selection. Familiar with ECO techniques and implementation. Good communicator who can accurately describe issues and follow them through to completion. Compensation and Benefits Base pay is determined within a range of $147,400 to $272,100, based on your skills, qualifications, experience, and location. You may also be eligible for discretionary bonuses, commission payments, and relocation assistance. Apple employees can participate in discretionary employee stock programs, purchase Apple stock at a discount, and receive comprehensive medical and dental coverage, retirement benefits, various discounts and free services. Educational expenses—including tuition—may be reimbursed for formal education related to advancing your career at Apple. Benefits and compensation subject to eligibility requirements and terms of the applicable plan. Equal Opportunity Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. #J-18808-Ljbffr
$150.4k - $277.6k
...SoC Physical Design Engineer, STA/Timing Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could...SuggestedRelocation- ...senior role focused on static timing analysis, synthesis, and low‑power... ...for complex WiFi SoCs. The position requires hands‑on experience with PrimeTime, Design Compiler, Genus, and multi‑corner... ...working with RTL, synthesis, and physical design teams in a dynamic environment...Suggested
$151.09k - $214.5k
A leading technology company in Cupertino, CA, is seeking a Physical Design Engineer responsible for implementing design partitions for complex Systems-on-Chip. The ideal candidate will have a Master's degree in Electrical Engineering and at least 2 years of relevant experience...Suggested- ...Position: Physical Design Engineer II (eInfochips Inc) Job Description: What... ...Execute synthesis, PNR, and STA for assigned partitions of... ...encompassing synthesis, PnR, timing convergence and physical verification... ...in System-on-Chip (SoC) design and implementation....SuggestedFull timeTemporary workWork at office
$170k
...description: We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs and... ...preferred. Key Responsibilities: Pre-layout STA for feasibility and timing constraint validation Chip/block-level...SuggestedLocal area$108k - $167.5k
...Senior Physical Design Engineer As a Senior Physical Design Engineer, you will be responsible for... ...& data analysis, scripting, STA or timing analysis. You will be reporting to Manager... ...Netlist-to-GDS flow including block/soc-level placement, clock tree synthesis...InternshipWork at officeFlexible hours$165k - $241.4k
...full product development—from design to qualification to... ...digital world. Your Impact As a Physical Design Engineer, you will play a key role in... ...optimize floor planning and timing, analyze and improve backend... ...Perform static timing analysis (STA), setup reviews, and sign-...Full timeTemporary workLocal areaFlexible hours- ...thinking and unusually hardworking Physical Design Engineer. As a member of our wide-... ...with architecture, CAD, timing, and logic design teams, with... ...in high PHY and/or SOC designs. Deep Knowledge about... ...understanding of Extraction and STA methodology and tools. Deep...
$210k - $250k
...the first silicon and system designed from the ground up for AI... ...speed training job completion times and tokens-per-second for... ...mode and has a world-class engineering team with decades of... ...Responsibilities Define the Physical Assembly of SOC. involving all aspects of physical...$181.1k - $318.4k
...Technologies group, you’ll help design and manufacture our next... ...a mix of strategic engineering along with hands-on experience in physical design and large chip... ...different domains like top, STA, block place and route.... ...and all aspects of timing, electrical and physical...Temporary workRelocation$181.1k - $318.4k
...Apple products!Apple’s Silicon Engineering Group (SEG) is hiring... ...engineers for CPU block-level physical design. Description As a CPU Physical... ...aspects of CPU floorplan, timing, power, reliability, and testability... ...logic Synthesis, PnR, STA and Power analysis tools,...Relocation$120k - $220k
...fundamentally change the design, economics,... ...highly experienced Senior Physical Design Engineer to join our ASIC implementation... ...of complex digital SoC designs from netlist... ...design, verification, and timing teams to deliver high-... ...Collaborate with the STA team to analyze and...Full timeWork at officeImmediate startVisa sponsorshipNight shift- ...Architect and micro-architect ASIC/SoC designs from initial concept through production,... ...resolve technical ambiguities, and ensure on-time, on-spec delivery. Lead design reviews... ...Boot, TrustZone, MMU/MPU, cryptographic engines, secure debug, TRNG, OTP/fuses, and...
$121.9k - $195k
## Physical IC Design EngineerApplylocations: USA-CA San Jose Innovation Drivetime type: Full timeposted... ...*Please Note:****1. If you are a first time user, please create your candidate... ...is searching for a Physical IC Design Engineer to join the Asic Products Division....Local areaRemote work$2,000 per month
...frontier intelligence. We co-design chips, racks, software, and manufacturing... ...and staffed by leading engineers, Etched is redefining the... ...is looking for exceptional Physical Design engineers to join our... ...implementation and verification, drive timing closure and PPA optimization,...Work at officeRelocation package- ...Physical Design Engineer Building AI chips that are hard-coded for individual model architectures. Seeking exceptional PD engineers to join... ...to GDSII sign-off ~ Experience with back-end design and timing closure on 3nm-7nm ~ Experience with UPF-based low power...
$230k - $280k
...builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows... ...The Role As a member of our tight knit physical design team, you will be working on the design... ...involves a combination of traditional ASIC/SoC physical design skills, packaging, power...$175.8k - $264.2k
...Responsible for all aspects of physical design verifications including:... ...verification methodology for SOC, full chip integration flows,... ...with process variation, various timing margins and derates, and detailed... ...with both Physical Design Engineers and foundry for new PDK...Full timeRelocation$220k - $350k
...About the role Own Full chip and Block timing methodologies and execution to-signoff of... ...our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI... ...AI-assisted tool flows to accelerate physical design timing convergence and signoff timelines...Full timeH1bVisa sponsorshipWork visa$140k - $170k
...- $170,000 Credo is engineering the future of high-speed... ...Cables(AECs) all designed for maximum performance... ...the Role As a Senior Physical Design Engineer, you will... ...for Credo SoC designs. This role involves... ...to GDSII. Focus on timing, power, and area (PPA)...Local area$164.47k - $232.19k
...Develops the logic design, register transfer... ..., area, and timing goals as well as design... ...design integrity for physical implementation.... ...features. Supports SoC customers to... ...Degree in Electrical Engineering, Computer Science,... ...RTL-to-GDSII flow, STA, and CDC Familiarity...Full timeInternshipLocal areaImmediate startShift work$120k - $220k
...fundamentally change the design, economics,... ...are seeking a Senior STA Methodology Engineer to join our ASIC design... ...own cross-functional timing methodology efforts across... ...for our cutting-edge SoC designs targeting 5G,... ...to design and physical design engineers WHAT...Full timeWork at officeImmediate startVisa sponsorshipNight shift$165k - $241.4k
...full product development—from design to qualification to production... ...multiple protocols and large-scale SoC architectures. Experience... ...work together across the physical and digital worlds. These solutions... ...Cisco for defined periods of time. U.S. employees are...Full timeTemporary workLocal areaFlexible hours$60k - $148.5k
...Job Title: Design Verification Engineer City: Santa Clara State/... ...environments for IP/subsystem/SoC level testing Develop... ...Mandatory Skills: VLSI Physical Place and Route. Experience... ...disability insurance, paid time off (inclusive of sick...Minimum wageLocal area- ...Job Title: SoC Design Verification Engineer Location: San Jose, CA Job Description: We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex SoCs. The role involves...Night shift
$130k - $155k
...goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we'... ...grid generation, place and route, timing, noise, physical verification, electromigration... ...issues in static timing analysis (STA), noise, logic equivalency, physical...Permanent employmentTemporary workWorldwideWeekend work$164.47k - $311.89k
...Intel is seeking a Senior Design Verification Engineer for the Silicon Chassis team... ...with enough breadth in RTL, physical design, and CAD to... ...in IP DV, and subsystem and SoC-level verification ~ Experience... ...allows employees to split their time between working on-site at...InternshipLocal areaImmediate startShift work- ...an adaptive, self-motivated design engineer to be part of a leading team... ...components. Guarantee quality/timely deliverables meeting project'... ...performance, low power FPGA/SOC. Combined Experience or... ...medical condition, mental or physical disability, national origin,...Work experience placement
- ...domain to satisfy functional, physical and testing design requirements. Engage with... ...Optimization and Ease of timing closure to innovate and implement... ...to GPU, CPU and SOC verification team, timing and... ...Qualifications BS in Electrical Engineering or equivalent experience (...Work experience placement
$100k
...our team and looking for contributors of all seniorities. Tenstorrent is seeking a passionate Physical Design Engineer with deep expertise in multi-voltage and low-power SoC design to join our team driving the next frontier of AI silicon. In this role, you will...Permanent employment
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