DFT Engineer

DFT Engineer – Associate III – Semiconductor Product Validation We are seeking a DFT Engineer with strong understanding of scan design, ATPG, fault models (stuck‑at, transition, path delay), and test compression techniques. Responsibilities Define and implement DFT architecture including scan, MBIST, LBIST, and boundary scan for ASIC/SoC designs Develop and integrate scan chains, compression techniques, and test points to achieve high fault coverage Perform ATPG pattern generation, simulation, and debug to meet coverage & quality goals Work closely with design, physical design, and verification teams to ensure DFT readiness across all design stages Execute DFT checks such as DRC, LVS, and timing closure in coordination with backend teams Debug silicon bring‑up issues related to test failures and yield improvement Analyze test coverage reports and implement strategies to improve fault coverage and reduce test time Support manufacturing test, including tester bring‑up, pattern validation, and failure analysis Develop and maintain DFT documentation, test plans, and sign‑off reports Required Qualifications Bachelor's or Master's degree in Electronics/Electrical Engineering or related field 5+ years of experience in DFT for ASIC/SoC development Hands‑on experience with industry‑standard DFT and ATPG tools such as Synopsys DFT Compiler, TetraMAX, or Cadence Modus Experience in MBIST/LBIST insertion and validation Familiarity with JTAG/IEEE 1149.x standards and boundary scan implementation Good knowledge of Verilog/SystemVerilog and scripting languages like Tcl or Python Understanding of physical design impact on DFT (timing, congestion, power) Strong debugging and problem‑solving skills Desired Skills Experience with low‑power DFT techniques and multi‑voltage domain designs Exposure to silicon bring‑up and yield analysis Knowledge of tester platforms like Advantest or Teradyne Experience working in advanced nodes (7nm/5nm or below) Strong communication and collaboration skills Ability to work in cross‑functional global teams Self‑driven with a proactive approach to problem‑solving Compensation Location: California Range: $65,000–$98,000 Benefits Full‑time employees receive 10 days paid vacation, 6 days paid sick leave, 10 paid holidays, and eligibility for paid bereavement leave and jury duty. 401(k) retirement plan with employer matching. Medical, dental, vision insurance and other company‑paid employee‑only benefits. Additional benefits may be available based on location. Equal Employment Opportunity Statement UST is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, status as a protected veteran, or any other applicable characteristics protected by law. UST reserves the right to periodically redefine roles and responsibilities based on organizational requirements and/or performance. #J-18808-Ljbffr