Senior Power Integrity Engineer - LPU Packaging

NVIDIA is now looking for a Senior Power Integrity Engineer to join our LPU Packaging team!NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people! Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent.What you’ll be doing:Define best‑in‑class power delivery design and optimization practices from die/package through board, tray, and rack levels for the full product development cycleOwn the PI specification and methodology for assigned products, defining PDN targets including impedance, droop, noise, and transient response for GPU, HBM, and high‑speed SerDesArchitect package‑level PDNs by collaborating with design teams on bump/ball maps, via structures, and decoupling strategies for FCBGA and 25D/3D integrationsDrive system‑level PI design, including board‑level PDN planning, decap placement, and VRM interfaces while co-optimizing with SI, thermal, and mechanical teamsPerform PI extraction and simulation for advanced packages and develop integrated chip–package–board co‑simulation flows using industry-standard toolsGenerate and deploy reusable PI models, such as SPICE, S-parameter, and IBIS-AMI, for use by internal and external partnersDefine and execute comprehensive lab validation plans to correlate measured impedance, noise, and droop against simulation data and specificationsDebug complex system‑level issues including rail noise, jitter‑induced errors, resets, and margin loss during hardware testing and validationWhat we need to see:MS or PhD in Electrical Engineering or a related field, or equivalent experience12+ years of relevant work experience in Power IntegrityA strong background in power integrity for high-current, low-voltage rails within large GPUs, ASICs, or CPUsProven ownership of the chip-package-board PDN design and sign-off processHands-on experience with FCBGA, 25D/3D integration, HBM, or similar high-power, high-pin-count packagesDirect experience in the co-design of bump/ball maps, power/ground planes, and decoupling capacitor networksProficiency with frequency-domain PDN impedance analysis and time-domain transient/droop simulation tools (eg, PowerSI, PowerDC, Sigrity, RedHawk, Totem, HFSS, SIwave, ADS, or SPICE)A deep understanding of board-level PDN design, including stack-up definition, plane partitioning, and VRM placement on high-layer-count accelerator boardsExperience in executing lab measurements using VNAs, oscilloscopes, and PDN analyzers to correlate measured noise and droop to original specificationsWays to stand out from the crowd:Demonstrated leadership of end-to-end PI for a major GPU, CPU, or ASIC program from initial concept through mass productionExperience with data center or cloud hardware, specifically regarding rack-level power distribution and how PI choices impact performance headroomBackground in co-designing SI and PI for high-speed interfaces like PCIe, NVLink, CXL, or Ethernet SerDes to mitigate jitter and noise couplingStrong communication skills with the ability to clearly explain complex PDN trade-offs and risks to both technical teams and program stakeholdersWith highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology industry's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working with us and our product lines are growing fast in some of the hottest state of the art fields such as Artificial Intelligence, Deep Learning, Autonomous Vehicles, and Robotics. We have a real passion for perfection and for building products that excite the imagination. If you share these values and have the experience and skills to participate, we would love to have you join our team.Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 196,000 USD - 310,500 USD for Level 5, and 232,000 USD - 368,000 USD for Level 6.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until July 28, 2026.This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.SummaryLocation: US, CA, Santa ClaraType: Full time