Senior Post Silicon Low Power Integration Engineer

NVIDIA Silicon Co-Design Group is looking for a versatile engineer to help redefine how low-power silicon validation and system bring-up are developed for next-generation AI and accelerated computing platforms. Our team sits at the intersection of silicon architecture, platform validation, firmware, telemetry, and productization. We build the methodologies, infrastructure, and workflows that take low-power features from architectural intent through silicon bring-up and into production readiness.This role is about scaling low-power validation using AI-powered analytics, intelligent automation, telemetry pipelines, and modern debug workflows. You will help transform how power validation, workload characterization, feature correlation, and silicon debug are accomplished across product generations. The payoff is that the systems, tooling, and methodologies you help build will directly influence the power efficiency, stability, and production readiness of NVIDIA products shipped at scale worldwide.What You'll Be Doing:Define the Power & Performance validation strategy across product lines, including power targets, rail budgets, and low-power feature validation methodologies.Build intelligent workload characterization frameworks that use telemetry, behavioral clustering, and AI-assisted analytics to improve validation coverage and expose power-state and data-path issues earlier in the development cycle.Define the instrumentation, counters, telemetry frameworks, and firmware hooks needed to support scalable silicon observability, automated validation, and AI-powered debug workflows prior to tapeout.Bring up and validate system-level low-power features across pre-silicon and post-silicon environments using sophisticated automation, data-driven validation methodologies, and generative AI-assisted debug techniques. Develop AI/ML-assisted infrastructure for telemetry analysis, anomaly detection, predictive validation analytics, workload optimization, automated triage, and cross-generation debug correlation.Partner closely with architecture, firmware, DV, HSIO, system integration, and data infrastructure teams to build scalable validation pipelines, intelligent dashboards, and modern engineering workflows for next-generation silicon platforms.Support manufacturing and customer-facing teams in resolving production and feature issues using telemetry-powered insights, automated analytics, and scalable debug methodologies.Work across hardware, software, firmware, and platform teams to drive low-power feature readiness from early architecture definition through silicon bring-up, validation, and product release.What We Need to See:BS/MS in EE, CE, CS, Systems Engineering, or equivalent experience.10+ years of experience in silicon characterization, low-power feature validation, system integration, or post-silicon productization.Strong understanding of silicon power behavior, Windows/Linux low-power states, firmware interactions, power/performance tradeoffs, and system-level validation methodologies.Experience building scalable automation, telemetry analytics, or AI-assisted engineering workflows for silicon validation, debug, or productization.Strong EE fundamentals, including digital design, computer architecture, power analysis, statistics, and scripting/programming skills.Hands-on experience with silicon bring-up, lab validation, debug methodologies, and hardware lab instrumentation.Familiarity with AI/LLM-assisted engineering workflows, intelligent automation frameworks, telemetry analytics, or data-driven debug infrastructure.Ways to Stand Out from the crowd:Experience applying AI/ML or LLM technologies to silicon validation, telemetry analytics, workload optimization, or debug automation.Background in platform power management technologies such as S0ix, ASPM, RTD3, Memory Self Refresh, or system-level power-state coordination.Experience building large-scale telemetry pipelines, automated validation dashboards, or intelligent observability infrastructure.Strong Python, data analytics, and automation framework development experience.Experience working across architecture, firmware, silicon validation, and manufacturing organizations to drive production readiness.With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the world’s most desirable employers in the technology field. We encourage you to join our team, which consists of some of the hardest-working people in the world working together to promote rapid growth. Are you passionate about joining an outstanding team supporting the latest in GPU and AI technology? If so, we want to hear from you.#LI-HybridYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until August 1, 2026.This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.SummaryLocation: US, CA, Santa ClaraType: Full time