STA Design Engineer: SoC Timing & Power Closure
$140k - $210kNutanix
Qualcomm is looking for a skilled engineer for their ASIC Implementation Team in San Diego, California. This role focuses on timing constraints development and power analysis for advanced semiconductor chips, requiring at least 4 years of ASIC design experience. Candidates should be proficient with tools such as Primetime and have scripting skills in Tcl, Perl, or Python. The company offers a competitive salary range of $140,000 to $210,000 along with additional benefits. #J-18808-Ljbffr Nutanix
Vacancy posted 2 days ago
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