Timing Design Engineer
$120.3k - $210.1kApple Inc.
Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something — you’ll add something. Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign‑off, STA and sign‑off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign‑off to achieve sign‑off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign‑off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis. Minimum Qualifications Bachelors of Science in Electrical Engineering. Preferred Qualifications Proven knowledge of the ASIC design timing closure flow and methodology. 2+ years of experience in writing ASIC timing constraints and timing closure. Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues. Hands on experience in timing/SDC constraints generation and management. Proficient in scripting languages (Tcl and Perl). Familiarity with synthesis, DFT and backend related methodology and tools. Strong communication skills are a pre‑requisite – you will be collaborating with many diverse groups at Apple. The ideal candidate will be a self‑starter and highly motivated to be successful at Apple. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $120,300 and $210,100, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr Apple Inc.
$140k - $210k
Qualcomm is looking for a skilled engineer for their ASIC Implementation Team in San Diego, California. This role focuses on timing constraints development and power analysis for advanced... ..., requiring at least 4 years of ASIC design experience. Candidates should be...Suggested$139.5k - $258.1k
SoC Physical Design Engineer, STA/Timing Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish...SuggestedRelocation$171.6k - $302.2k
...company in California is seeking an experienced SoC Physical Design Engineer responsible for the physical implementation of design partitions... ...You will work closely with design teams to debug and improve timing, create methodologies, and perform deep analysis of timing...Suggested$140k - $210k
Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS... ...looking for skilled engineers to focus on timing constraints development, power analysis,... ...timing analysis.Collaborate closely with RTL design and physical design teams to identify...SuggestedWork experience placementWork from home$171.6k - $302.2k
...Wireless Design Engineer Come join Apple's growing wireless silicon development team. Our wireless SOC organization is responsible for... ...to ensure lint-free and CDC/RDC clean design Synthesis and timing constraints Power analysis and optimization Collaboration...SuggestedRelocation$121.65k - $194.3k
...Arcadis is the world's leading company delivering sustainable design, engineering, and consultancy solutions for natural and built assets. We... ...and wastewater facilities. Arcadis offers benefits for full time and part time positions. These benefits include medical, dental...Full timePart timeWork at officeLocal area$120.3k - $210.1k
Wireless PHY Design Verification Engineer Join Apple's Wireless Connectivity team developing state-of-the-art WiFi SoCs that power hundreds of millions... ...PHY Design Verification Engineer, you'll ensure first-time-right silicon success through sophisticated testbenches, comprehensive...WorldwideRelocation$128k - $192k
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > Modem... ...seeking a highly skilled Modem Hardware Design Verification Engineer to join our advanced... ...firmware, and RTL design teams to ensure first‑time‑right silicon for high‑performance modem...Work experience placement$220k
Principal SoC Full-Chip Implementation Physical Design & Verification Engineer job at Acara Solutions. San Diego, CA. Acara Solutions has been providing... ...planning, bump design, Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification. The entire...$104.1k - $173.4k
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS... ...General Summary Role: Familiarity with RTL design in Verilog and SystemVerilog. Develop verification... .... Will need to be in San Diego full time, 5 days a week. Security and citizenship...Full timeWork experience placementFlexible hours$85k - $120k
Design Engineer Supervisor: Engineering Manager Classification: Full-time, exempt Location: San Diego, CA. Office The Design Engineer is responsible for the design coordination, planset production, and permitting of an energy project. For new construction projects, the...Full timeWork experience placementWork at officeLocal areaFlexible hours$148.3k - $222.5k
Company Qualcomm Technologies, Inc. Job Area Engineering Group, Engineering Group > Camera... ...Camera HW team is looking for a strong ASIC design engineer for an exciting opportunity to... ...Domain Crossing checks, Synthesis, Timing analysis, Low power checks Preferred Qualifications...Work experience placementWork from home$120.3k - $210.1k
...particular emphasis on highly energy-efficient design and new technologies that transform the... ...by a world-class vertically integrated engineering team spanning RF/Analog architecture,... ...areas as well as thriving during crisis times, we encourage you to apply. Description...Relocation package$163.3k - $290.1k
Standard Cell Design Methodology & Flow Engineer Do you have passion to join a world‑class Digital Design Engineering group and take imaginative and... ...sophisticated Machine Learning models to study the circuit trends in timing, power, and area, and to potentially detect quality...Relocation$120.3k - $210.1k
...particular emphasis on highly energy‑efficient design and new technologies that transform the... ...by a world‑class vertically integrated engineering team spanning RF/Analog architecture,... ...and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of...Relocation$171.6k - $302.2k
...team? The wireless RFIC team architects, designs, and validates radio transceivers... ...by a best-in-class vertically integrated engineering team spanning RF/Analog architecture and... ...requirements at IC level. Familiarity with timing analysis tools (Nanotime, Primetime). Direct...Relocation$98.5k - $147.7k
Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS... ...ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify... ...level design to synthesis, place and route, timing and power use, and verification or similarly...Work experience placementImmediate startWork from home$127.2k - $190.8k
Overview Qualcomm Technologies, Inc. - Engineering Group, DSP Architecture and Design. A variety of high performance, low power Hexagon/NPU cores are at the... ...understanding of RTL design, synthesis, static timing analysis, PLDRC, clock domain crossing, and low power...Work experience placement- Job Details Job Title: Design Engineer Location: San Diego, CA Zip Code: 92123 Duration: 7 Months Pay Rate: TBD Start Date: Immediate... ...dental, vision, life insurance, 401(k), education assistance, paid time off including PTO, holidays, and any other paid leave required...For subcontractorLocal areaImmediate start
$120.3k - $210.1k
We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team! Our team specializes in building next generation... ...evaluation, correlation, and characterization Concepts of timing closure and related industry tools (e.g., Nanotime, Primetime)...Relocation$171.6k - $302.2k
Description We're looking for a Cellular ASIC Design Engineer, where you will architect and implement protocol processing hardware for next... ...in SystemVerilog and Verilog. Skilled in with synthesis and timing analysis tools. Experience with low‑power design techniques....Relocation$140k - $170k
Johnson Service Group is seeking a Design Engineer III for a temp to perm position located in San Diego, CA. Salary range: $140K - $170K DOE... ...and that additional tasks may be assigned to the employee from time to time. The scope of the job may change as necessitated by...Weekly payPermanent employmentTemporary workFor subcontractor- ## Job Description# Physical Design Engineer* The client is developing next-generation silicon to power a global Low Earth Orbit (LEO) satellite... ...clock distribution* Perform and resolve congestion analysis, timing closure, and physical optimization.* Execute IR drop and...
$97.7k - $171k
...transform the world for good. Your impact We’re seeking mid-level design engineers with experience in sediment remediation design for federal and... ...of your work will be office-based, but you may spend some time in the field supporting or overseeing the gathering of design...Full timeFor contractorsFor subcontractorWork at officeRemote work$139.5k - $258.1k
...Silicon Technologies group, you’ll help design and manufacture our next-generation, high... ...every day. Description As a GPU Design Engineer, you will be responsible for delivering high... ...graphics IP that meets our performance, timing, and area goals. You will explore design...Relocation- ...both in and out of the office. We are looking for an Antenna Design Engineer to join our hardware team in San Diego or San Francisco. This... ...prototype builds in both Asia, Europe, and North America: ~15-20% of time yearly Qualifications Bachelor’s or Master’s degree in...Work at officeLocal areaOverseasFlexible hours
$201.3k - $367.4k
Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation methodology for integrated circuits... ...methodologies, and standards for synthesis, place‑and‑route, timing closure, and signoff processes; develop and optimize EDA tool...Relocation$120.3k - $210.1k
...opportunity for a results-oriented and highly motivated DDR Design Engineer.As a member of our dynamic group, you will have the rare and... ...will include driving functional and code coverage as well as timing closure for your designs and supporting silicon bring-up, performance...Relocation$85k - $100k
RASIRC is seeking a passionate and dynamic Design Engineer II to join our team. If you're someone who thrives in a fast-paced environment, enjoys... ...exchange for employee health insurance for employees. Paid Time Off 401k with company match Why You Should Join Us: “RASIRC...Permanent employmentWork experience placementLocal areaRelocationRelocation package$67.7k - $91.9k
Design Engineer Latitude 33 Planning & Engineering is seeking a Design Engineer to design and review plans and specifications for residential... ...projects. Seniority Level Entry level Employment Type Full-time Job Function Engineering and Information Technology Industries...Full time
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