Sign up to access all features of our service.
  • Job search
  • Favorites
  • Create a CV
    New
  • Salaries
  • Subscriptions

Sr. Staff Physical Design Engineer, EMIR Analysis & Signoff

$237k - $296k
Full-time

Rivian

About Rivian

Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. 

As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations. 


Role Summary

We are seeking a highly skilled Physical Design Engineer specializing in Power Integrity (PI) and Signoff Analysis. In this role, you will be responsible for ensuring the electrical reliability and performance of our next-generation SoCs. You will bridge the gap between physical implementation and electrical verification, focusing on static/dynamic power analysis, electromigration (EM), and IR drop mitigation to ensure robust silicon performance, leading to a successful tapeout and production silicon.


Responsibilities

1. Power Analysis & Optimization

  • Perform Static IR Drop analysis to validate the robustness of the power grid (PG) and ensure connectivity.
  • Conduct Dynamic Voltage Drop (DVD) analysis using switching activity (VCD/FSDB) to identify hotspots during peak functional bursts.
  • Work closely with the RTL and Architecture teams to optimize power consumption at the block and top levels.

2. Electromigration (EM) & Reliability

  • Execute Signal EM and Power EM analysis to ensure long-term interconnect reliability.
  • Validate current density limits across various metal layers and vias, ensuring compliance with foundry design rules (LVS/ERC).
  • Implement fixes for EM violations through wire widening, via doubling, or rerouting.

3. Power Integrity Signoff

  • Drive the signoff flow for deep sub-micron process nodes (e.g., 5nm, 3nm, and below).
  • Analyze the impact of decoupling capacitor (Decap) placement on transient noise and voltage stability.
  • Collaborate with the Physical Design team to optimize the Power Grid (PG) density versus routing congestion.

4. Methodology & Flow Development

  • Develop and enhance automated scripts (Tcl/Python) to streamline PI analysis and reporting.
  • Stay updated on the latest EDA tool features and foundry requirements to improve analysis accuracy and turnaround time.
  • Working knowledge of UPF specification in Power Intent design, implementation, and verification of power gating, level shifter, and isolation.
  • Define EM-IR signoff requirements and sign-off methodology.
  • Define and support Static and Dynamic, thermal, electro-migration, peak current, di/dt, and effective resistance analysis
  • Develop and support Chip-package-Co-Analysis (CPA) and Chip-Power-Model (CPM) on-die model for package & die co-design analysis
  • Solid experiences in EM-IR sign-off with successful tape out track records
  • Excellent hand-on experience in voltage drop analysis using Redhawk-SC
  • Excellent hand-on experience and debugging skills of finding root cause of voltage drop and EM issues
  • Solid background in EM-IR fundamentals, analytical aptitude and excellent attention to detail

Qualifications

  • BS/MS in Electrical Engineering
  • 10+ years of extensive physical design experiences at both block and sub-chip level, as well as full-chip level is a plus.
  • Deep understanding of Power Delivery Networks (PDN) and the physics of IR drop.
  • Good knowledge of PI and EM-IR sign-off requirements.
  • Proficiency in industry-standard PI/Signoff tools: Ansys RedHawk-SC, Cadence Voltus, or Synopsys PrimePower/Rail.
  • Experience with Multi-Voltage (MSV) designs and UPF/CPF power intent.
  • Knowledge of Chip Package Co-Design (CPM) and system-level power integrity.
  • Experience in high-performance designs (AI) where dynamic power is a critical constraint.
  • Solid experiences in timing (STA) impacts of voltage droop, and thermal effects.
  • Programming: Strong scripting skills in Tcl, Python, or Perl for flow automation.
  • Soft Skills: Strong analytical problem-solving abilities and the ability to work in a cross-functional environment (Front-end, PD, and Package teams).

Pay Disclosure

The listed base salary range for this role is $237,00 - $296,000 for San Francisco Bay Area based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs.

We offer a comprehensive package of benefits for full-time and part-time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits including life, medical, dental, vision, short-term disability insurance, and long-term disability insurance to eligible employees. You may also have the opportunity to participate in Rivian’s 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements. Full-time employee coverage is effective on their first day of employment. Part-time employee coverage is effective the first of the month following 90 days of employment. More information about benefits is available at rivianbenefits.com.

Equal Opportunity

Rivian is an equal opportunity employer and complies with all applicable federal, state, and local fair employment practices laws. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, sex, sexual orientation, gender, gender expression, gender identity, genetic information or characteristics, physical or mental disability, marital/domestic partner status, age, military/veteran status, medical condition, or any other characteristic protected by law.

Rivian is committed to ensuring that our hiring process is accessible for persons with disabilities. If you have a disability or limitation, such as those covered by the Americans with Disabilities Act, that requires accommodations to assist you in the search and application process, please email us at  View email address on ev.careers .

Candidate Data Privacy and Technology

Rivian may collect, use and disclose your personal information or personal data (within the meaning of the applicable data protection laws) when you apply for employment and/or participate in our recruitment processes (“Candidate Personal Data”). This data includes contact, demographic, communications, educational, professional, employment, social media/website, network/device, recruiting system usage/interaction, security and preference information. Rivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law.

Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian’s service providers, including providers of background checks, staffing services, and cloud services.

Rivian may transfer or store internationally your Candidate Personal Data, including to or in the United States, Canada, the United Kingdom, and the European Union and in the cloud, and this data may be subject to the laws and accessible to the courts, law enforcement and national security authorities of such jurisdictions. 

How We Use AI in Our Hiring Process: To ensure transparency, we want candidates to know that Rivian uses iCIMS Talent Cloud Artificial Intelligence (TCAI) and AI-enabled tools to assist with screening, reviewing, organizing and highlighting profiles and applications that match the key requirements for each role.

AI does not make hiring decisions: Qualified candidate applications are reviewed by a member of our team, and all decisions throughout the process are made by humans. We use AI to support efficiency and consistency, not to replace human judgment. We are committed to a fair, thoughtful, and equitable experience for every candidate.

Participation in AI profile matching is entirely voluntary. If you prefer that your profile not be used in this process, you can opt out at any time. Opting out means your profile will be excluded from automated matching and will not be surfaced for additional roles through this system. Your current application remains active and will not be affected in any way.

Please note that we are currently not accepting applications from third party application services.

Vacancy posted 2 days ago
Similar jobs that could be interesting for youBased on the Sr. Staff Physical Design Engineer, EMIR Analysis & Signoff in California vacancy
  • $237k - $296k

     ...protect it for future generations.  Role Summary We are seeking a highly skilled Physical Design Engineer specializing in Power Integrity (PI) and Signoff Analysis. In this role, you will be responsible for ensuring the electrical reliability and performance... 
    Senior
    Full time
    Contract work
    Temporary work
    Part time
    Local area
    Shift work

    Rivian

    California
    2 days ago
  • $175k - $280k

     ...goal of enabling human life on Mars.SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)At SpaceX we’...  ...drop, logic equivalency and other signoff checks)Develop/improve physical design...  ...closure issues in static timing analysis (STA), noise, logic equivalency, physical... 
    Senior
    Permanent employment
    Temporary work
    Worldwide
    Weekend work

    SpaceX

    Palo Alto, CA
    2 days ago
  • $136k - $218.5k

     ...now looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic and growing team...  ...synthesis, routing, physical optimization, signoff, and ECOs.Demonstrated success...  ..., and full-chip level Static Timing Analysis, timing-constraint development, and... 
    Senior
    Full time

    Nvidia

    Santa Clara, CA
    6 days ago
  • $159.2k - $215.3k

     ...• Work with RTL/logic designers to drive architectural...  ...performance-area tradeoffs for physical design closure • Drive...  ..., congestion analysis, timing closure, IR drop...  ...other physical design engineers as well as with the...  ...employees, supervisors, and staff; adhere to standards... 
    Senior
    Permanent employment
    Local area
    Flexible hours

    Amazon

    San Diego, CA
    4 days ago
  • $138k - $206k

     ...leader whose innovative designs are pushing the...  ...hardware and software engineers to identify and address...  ....What You’ll DoOwn the physical implementation of memory...  ....Perform static timing analysis (STA), constraint development, and signoff, resolving setup/hold timing... 
    Senior
    Work at office
    Flexible hours
    Night shift

    Samsung Semiconductor

    San Jose, CA
    3 days ago
  • $183k - $247.6k

     ...services.We are seeking an experienced Sr. Physical Design STA Engineer to build the next generation of our...  ...block and full-chip level static timing analysis• Write, debug & validate timing...  ...with other employees, supervisors, and staff; adhere to standards of excellence despite... 
    Senior
    Full time
    Local area
    Flexible hours

    Amazon

    Cupertino, CA
    1 day ago
  • $183k - $247.6k

     ...with 4+ years in Electrical Engineering or Computer Science. We need...  ...fundamentals in timing analysis. We require at least 3 years...  ...an understanding of ASIC physical design from RTL to GDSII. We require...  ...are hiring an experienced Sr. Physical Design STA Engineer... 
    Senior
    Full time

    Annapurna Labs (U.S.) Inc.

    Cupertino, CA
    6 days ago
  • $82.08k - $193.44k

     ...At Capgemini Engineering, the world leader in engineering services,...  ...you’re considering As a Physical Design Engineer , you will work on...  ...Support CDC, static timing analysis, parasitic-aware simulation,...  ...readiness, including design signoff, foundry interaction, and alignment... 
    Senior
    Full time
    Local area

    Capgemini

    Santa Clara, CA
    a month ago
  • $175.8k - $312.2k

     ...group, you'll help design and manufacture...  ...looking for passionate engineers to join our team....  ...to solve key physical design challenges....  ...implementation and signoff. - Creating flows...  ...and static timing analysis (STA). - Driving EDA...  ...physical verification, EMIR. Hands on... 
    Full time
    Relocation

    Apple

    Santa Clara, CA
    4 days ago
  • $121k - $205k

     ...and advance faster than ever.As a SoC Physical Design Engineer in the Heterogeneous Integration Group...  ...(performance, power, area) and robust signoff collateral for tape-out. This is a hands...  ...silicon behavior with PD/STA/power analysis.Identify flow gaps and improve productivity... 
    Full time
    Local area
    Immediate start
    Night shift

    Micron

    Folsom, CA
    1 day ago
  • $168k - $264.5k

     ...on the world.NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer, PPA Fusion Compiler to join our outstanding Networking...  ...developing flow and tool methodologies for P&R, timing analysis and closure, convergence in IR/Signal-EM, power and noise... 
    Senior
    Full time

    Nvidia

    Santa Clara, CA
    4 days ago
  • $168k - $264.5k

    We are now looking for a Senior Physical Design Engineer. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU...  ...assembly and P&R, timing closure.Craft designs for static timing analysis, power and noise analysis and back-end verification.What we... 
    Senior
    Full time

    Nvidia

    Santa Clara, CA
    4 days ago
  • $168k - $264.5k

     ...can make a lasting impact on the world.We are looking for a physical design engineer to be a part of NVIDIA’s physical design (PD) methodology...  ...SAIFs for power optimizationSolid understanding of EM and IR analysis and closureUnderstanding of synthesis, hierarchical design,... 
    Senior
    Full time
    Remote work

    Nvidia

    Santa Clara, CA
    4 days ago
  • $136k - $218.5k

     ...intelligence.We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team. If you...  ...asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.Help in all... 
    Senior
    Full time
    Shift work

    Nvidia

    Santa Clara, CA
    10 hours ago
  • $136k - $218.5k

     ...CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on-chip...  ...see:Master’s Degree in Electrical Engineering, Computer Engineering or Computer...  ...on synthesis experience, timing analysis, floor-planning and in-depth knowledge... 
    Senior
    Full time

    Nvidia

    Santa Clara, CA
    1 day ago
  •  ...Physical Design Engineer - Location: San Jose OR Irvine, CA Our client develops specialized semiconductor solutions...  ...grid creation, place and route, timing analysis, noise analysis, physical verification, EM/IR checks, and signoff tasks. Enhance methodology and automation:... 
    Full time
    H1b
    Visa sponsorship
    Relocation package

    Gyga Force Co

    San Jose, CA
    1 day ago
  • $100k

     ...of all seniorities.Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across...  ..., bump/RDL strategies, and reliability analysis (IR drop, EM), with solid understanding of advanced... 
    Permanent employment

    Tenstorrent

    Santa Clara, CA
    3 days ago
  • $180k - $220k

     ...Physical Design - Cad LeadEfficient is developing the world's most energy...  ...in a newly formed hardware engineering group and is the seed hire for...  ...end to end build and signoff flows.Build regression frameworks...  ...constraints for static timing analysis (synthesis, pre/post?cts,... 

    Efficient Computer Service LLC

    San Jose, CA
    5 days ago
  • $2,000 per month

     ...frontier intelligence. We co-design chips, racks, software...  ...staffed by leading engineers, Etched is redefining...  ...P&R, clocking, timing analysis, physical verification, and sign...  ...achieve final timing signoff for tapeout. Own...  ...all of our technical staff to contribute to both... 
    Work at office
    Relocation package

    Etched

    San Jose, CA
    27 days ago
  • $167k - $275k

     ...unique combination of design, development, and fabrication...  ...of digital design engineers, driving architecture...  ..., verification, physical design, DFT, firmware,...  ...architectural tradeoff analysis and performance optimization...  ...Drive design reviews, signoff readiness, and cross-... 
    Senior
    Full time
    Local area

    Globalfoundries

    Santa Clara, CA
    2 days ago
  • $250.6k - $362.6k

     ...full product development—from design to qualification to...  ....Your ImpactCollaborate with physical design teams to identify high...  ...triage, Congestion root-cause analysis, floorplan suggestions.Evaluate...  ...QualificationsBachelor’s degree in Engineering and 15+ years of ASIC related... 
    Full time
    Temporary work
    Local area
    Flexible hours

    CISCO Systems

    San Jose, CA
    4 days ago
  • $100k

     ...seniorities.We’re looking for a Timing Engineer to join our silicon team. In this role, you’ll drive static timing analysis and closure for complex, high-performance designs. You’ll collaborate closely with logic, DFT, and physical design teams to debug constraints,... 
    Permanent employment

    Tenstorrent

    Santa Clara, CA
    4 days ago
  • $140k - $229.8k

    Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS...  ...actively seeking candidates for several physical design engineering positions in our SOC and...  ...floorplanning, power planning, IR drop analysis, cell placement, multi-mode & multi-... 
    Work experience placement
    Work from home

    Qualcomm

    Santa Clara, CA
    4 days ago
  • $100k

     ...of all seniorities.Tenstorrent is seeking a highly skilled Physical Design Engineer to drive the critical Die-to-Die (D2D) Physical Implementation...  ...and verification, including full STA (setup/hold), SI analysis (crosstalk, IR drop), and achieving sign-off quality DRC/LVS... 
    Permanent employment
    Remote work

    Tenstorrent

    Santa Clara, CA
    3 days ago
  • $230k - $280k

     ...transforming key workloads with ultra high-speed inference.About The RoleAs a member of our tight knit physical design team, you will be working on the design and analysis of 3D integrated products. This role involves a combination of traditional ASIC/SoC physical design... 

    Cerebras Systems

    Sunnyvale, CA
    4 days ago
  • $129.4k - $207k

     ...before you apply.Job Description:Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group at our main campus...  ...; preferable in-depth experience in top-level STAEM/IR Analysis,Place and RouteClock Tree Synthesis; experience with custom... 
    Full time
    Local area
    Remote work

    Broadcom

    San Jose, CA
    4 days ago
  • $100k

     ...seniorities.Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU...  ...-voltage domain designs.Mastery of timing closure, EM/IR analysis, and physical verification at the chip level.What You Will... 
    Permanent employment

    Tenstorrent

    Santa Clara, CA
    2 days ago
  • Position:Physical Design Engineer II (eInfochips Inc)Job Description:What You'll Be Doing:Execute synthesis...  ...to resolve implementation and signoff issues across your blocks.Help close EM...  ...route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical... 
    Full time
    Work at office

    Arrow ECS

    San Jose, CA
    4 days ago
  • $170k - $220k

    Job description: We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs and delivers...  ...timing optimizationSign-off tasks: RC extraction, STA, IR-drop analysis, and physical verificationCustomer meetings and technical... 
    Local area

    Affinity Executive Search

    San Jose, CA
    4 days ago
  • $168k - $264.5k

     ...self-starting Senior Circuit Design Engineer to join our dynamic and...  ...solutions.Drive the design and physical implementation of analog/mixed...  ...IPs.Perform detailed analysis to ensure good reliability and...  ...standard EDA tools for AMS, EMIR, self-heating, aging, SOA, floating... 
    Senior
    Full time

    Nvidia

    Santa Clara, CA
    10 hours ago

Do you want to receive more vacancies?

Subscribe and receive similar vacancies to Sr. Staff Physical Design Engineer, EMIR Analysis & Signoff. Be the first to apply!