Sign up to access all features of our service.
  • Job search
  • Favorites
  • Create a CV
    New
  • Salaries
  • Subscriptions

Senior ASIC/VLSI Design Engineer - RTL, DFT & Bring-up

Retym Israel Ltd

A tech company in Cupertino is seeking an experienced ASIC/VLSI Design Engineer to design innovative communication systems. The role involves collaboration with multiple teams, RTL coding, and optimization of design for performance. Candidates should have over 5 years in digital design with strong Verilog/System-Verilog skills and educational background in electrical or computer engineering. This position allows creativity and independence in a cutting-edge environment. #J-18808-Ljbffr Retym Israel Ltd

Vacancy posted 2 days ago
Similar jobs that could be interesting for youBased on the Senior ASIC/VLSI Design Engineer - RTL, DFT & Bring-up in Cupertino, CA vacancy
  • ## ASIC/VLSI Design EngineerAustin, Texas · Full-time#### About...  ...VLSI Design Engineers/Micro-architects.As an...  ...architecture definition*** **RTL coding (using Verilog/...  ...coverage closure.* **DFT team:** Ensure design...  ...Participate in Silicon Bring-up and Validation (optional... 
    Suggested
    Full time

    Retym Israel Ltd

    Cupertino, CA
    4 days ago
  •  ...libraries like UVM 10+ years of ASIC design verification experience...  ...Collaborate with architects, hardware engineers, and firmware engineers to...  ...Design for Test methodologies and DFT verification experience is a...  ...in debugging firmware and RTL code using simulation tools KEY... 
    Senior

    Infobahn Softworld Inc

    Santa Clara, CA
    4 days ago
  • $150k - $220k

     ...will fundamentally change the design, economics, manufacturing...  ...life. We are seeking a Senior ASIC Design Engineer to join our processor subsystem...  ...at the intersection of RTL design and functional verification...  ...and hands-on experience bringing together complex IP in a... 
    Senior
    Full time
    Work at office
    Immediate start
    Visa sponsorship
    Night shift

    E-Space

    Saratoga, CA
    9 days ago
  • $160k - $312k

    A leading automotive company is seeking an ASIC RTL Design Engineer in Palo Alto, CA. This role involves specifying and designing microarchitectures for cutting-edge AI accelerators, ensuring high-performance and power-efficient RTL design. Candidates should have a degree... 
    Senior

    Tesla Motors, Inc.

    Palo Alto, CA
    1 day ago
  • Hybrid // Physical Design Engineer-ASICs, SoCs, VLSI Physical Design Engineer-ASICs, SoCs, VLSI Full time Sunnyvale...  ...and electrical verification. DFT Integration - Work with Design for Test...  ...chain connectivity and testability. Seniority level Mid-Senior level Employment type... 
    Suggested
    Full time

    Talent Groups

    Sunnyvale, CA
    4 days ago
  • $170k - $230k

     ...life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...  ...the software that brings it all together. We’ve...  ...targets, and explore RTL/design tradeoffs Resolve...  ...design Knowledge of DFT/Scan/MBIST/LBIST and...  ...Design Engineer/Senior: $170,000.00 - $230,0... 
    Senior
    Permanent employment
    Temporary work
    Worldwide
    Weekend work

    SpaceX

    Sunnyvale, CA
    1 day ago
  • $160k - $414k

     ...innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference...  ...AI Hardware team is looking for a Senior ASIC RTL Design Engineer to work on industry...  ...Design for synthesis What You'll Bring High performance (low latency, high... 
    Senior
    Hourly pay
    Full time
    Temporary work
    Flexible hours

    Tesla Motors, Inc.

    Palo Alto, CA
    1 day ago
  •  ...adaptive, self-motivative Design Verification Engineer to join our growing...  ...help our experts in RTL, FW, circuit, and...  ...like UVM 10+years of ASIC design verification experience...  ...methodologies and DFT verification...  ...Electrical Engineering Seniority level Mid-Senior level... 
    Contract work
    Work at office
    2 days per week
    3 days per week

    Infobahn Softworld Inc

    Santa Clara, CA
    4 days ago
  •  ...will contribute to the ASIC (chip) design for high-performance...  ...Design Team, you will help bring to life cutting‑edge...  ...teams, and product engineers to achieve first‑pass...  ...candidate will work with senior silicon design...  ...implementation Front‑end RTL design and integration... 
    Senior

    AMD

    Santa Clara, CA
    1 day ago
  • $130k - $220k

     ...technology company in Santa Clara seeks a highly skilled engineer for microarchitecture design and ASIC development. The role involves working on innovative technology solutions with responsibilities including RTL coding, timing closure, and design verification.... 
    Senior

    Elastics.cloud, Inc.

    Santa Clara, CA
    2 days ago
  • Tesla is seeking experienced engineers for its AI Hardware team in Palo Alto, who will focus on micro-architecture specification and design, delivering efficient RTL designs, and collaborating with cross-functional teams to enhance AI capabilities. Focusing on high performance... 
    Senior

    Tesla

    Palo Alto, CA
    1 day ago
  • $160k - $312k

     ...hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference...  ...team is seeking a highly motivated ASIC RTL Design Engineer with a...  ...physical design and verification teams to bring designs from concept to silicon, with... 
    Hourly pay
    Temporary work
    Flexible hours

    Tesla

    Palo Alto, CA
    1 day ago
  • $100k - $166.75k

    We are looking for an ASIC Clocks Design Engineer to join the team. Our team crafts...  ...new Clocking topologies in RTL. Collaborate with Physical...  ...verification team, timing and DFT teams. Get involved in end‑...  ...and all the way to Silicon bring‑up. What we need to see: Bachelor... 

    Nvidia Corporation

    Santa Clara, CA
    1 day ago
  • $195k - $226k

    Ambarella Inc is seeking an experienced VLSI designer to work on highly differentiated SoC designs that influence the next generation of AI...  ...Responsibilities include designing video processing systems, optimizing RTL, and participating in chip testing. A Master’s degree and 5-10... 

    Ambarella Inc

    Santa Clara, CA
    1 day ago
  •  ...Provider. Prodapt ASIC services is the...  ..., Offshore design center (ODC) or...  ...ASIC BU: SoC/ASIC RTL Design, UVM based...  ...based validation, DFT, RTL2GDSII, Physical...  ...porting, Board bring up. We are looking for a Senior Design...  ...collaborate with design engineers to resolve... 
    Senior

    Prodapt

    Sunnyvale, CA
    6 hours ago
  • $136k - $218.5k

     ...the future of computing. As a Senior ASIC Power Engineer in our Santa Clara, CA...  ...methodologies, power feature bring‑up on silicon, and post‑Si power...  ...convergence across RTL, Gates, and Silicon. Validate...  ...dynamic characteristics in VLSI circuits. Strong fundamentals... 
    Senior
    Work experience placement
    Work at office

    NVIDIA

    Santa Clara, CA
    1 day ago
  • $145k - $234.5k

    Senior ASIC Design Verification Engineer (Hardware) Senior ASIC Design Verification Engineer (Hardware) Direct message the job poster from Palo Alto Networks...  ...114,000.00-$166,000.00 3 days ago Senior ASIC FrontEnd (RTL) Design Engineer Senior Mechanical Design Verification... 
    Senior
    Full time
    Casual work
    Work at office

    Palo Alto Networks

    Santa Clara, CA
    1 day ago
  • $250k - $300k

     ...About the Role As a senior front‑end design engineer, you will be a key part...  ...deep expertise in RTL design and integration...  ...and system teams to bring innovative semiconductor...  ...Verification and DFT teams to achieve the...  ...managing an external ASIC vendor through the product... 
    Senior

    Cerebras

    Sunnyvale, CA
    1 day ago
  • $175k - $275k

     ...Role As a lead front-end design engineer, you will be a key part...  ...deep expertise in RTL design and integration,...  ...management of external ASIC vendor. You will collaborate...  ...and system teams to bring innovative semiconductor...  ...Design verification and DFT teams for achieving the... 

    Cerebras Systems

    Sunnyvale, CA
    4 days ago
  • Intel is looking for an experienced engineer to develop logic designs and RTL coding for SoC systems. This position demands 7+ years of experience in ASIC/SoC development, working closely with verification teams, and mentoring junior engineers. You will be part of a collaborative... 
    Senior
    Remote work

    Intel

    Santa Clara, CA
    1 day ago
  • $174k - $352.5k

    This role has been designed as ‘Hybrid’ with an expectation...  ...modifies and evaluates VLSI components and hardware...  ...closure. Fix timing in RTL to meet the frequency...  ...college-grad/junior engineers and interns. Recommended...  ...tools used in typical ASIC development process is... 
    Work experience placement
    Work at office
    2 days per week

    Hewlett Packard Enterprise

    Sunnyvale, CA
    1 day ago
  • $100 - $105 per hour

    A leading Technology Consulting firm is urgently seeking a Design Engineer V specializing in Power ASIC Engineering for a hybrid role in Sunnyvale, CA. Candidates should have 10 years of experience in ASIC design, particularly power estimation and physical design. Key... 
    Senior
    Contract work
    Immediate start

    Pyramid Consulting, Inc

    Sunnyvale, CA
    1 day ago
  • $180k - $210k

     ...per year Credo is engineering the future of high-...  ...Cables(AECs) all designed for maximum performance...  ...As a Principal ASIC Design Engineer, you...  ...design, including RTL implementation and...  ...collaborate with PD, DFT, STA, and...  ...system teams for chip bring-up and validation.... 

    Credo Semiconductor, Inc.

    San Jose, CA
    4 days ago
  • $160k - $312k

    Tesla in Palo Alto, CA, is seeking an ASIC RTL Design Engineer to join their AI Hardware team, which pioneers AI hardware innovation. The role involves microarchitecture specification, designing for performance and efficiency, and collaborating across teams to meet design... 

    Tesla

    Palo Alto, CA
    1 day ago
  • $116k - $189.75k

    We are now looking for an ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers...  ...performance, area and power efficient RTL to achieve design targets....  ...architects, designers, verification and VLSI teams to craft the industry's top performing... 

    NVIDIA

    Santa Clara, CA
    1 day ago
  • $120k - $243k

    This role has been designed as ‘Onsite’ with an expectation...  ...routers and switches. Bring your passion and there...  ...in building high‑speed ASICs, from specifications to...  ...and fix timing in RTL to meet the frequency target...  ...to new college‑grad engineers and interns. Recommended... 
    Work experience placement
    Work at office

    Hewlett Packard Enterprise

    Sunnyvale, CA
    1 day ago
  • $80 - $90 per hour

     ...major portions of the design and implementation...  ...in silicon bring-up for features owned...  ...proven track record of ASIC design on several...  ...in Designing RTL block for an SOC....  ...clear and concise engineering documentation. Ability...  ...s degree required Seniority level Seniority... 
    Contract work

    Infotree Global Solutions

    Santa Clara, CA
    4 days ago
  • $120k - $200k

    ASIC/SOC Silicon Physical Design Engineer Mountain View, CA MatX's mission is to...  ...allowed by physics, bringing the world years ahead...  ...fullchip designs from RTL to GDSII Own entire...  ...with the Design, DFT, and other Physical...  ...broad ranges for mid/senior candidates reflect greater... 
    Full time
    Work experience placement
    Local area

    MatX

    Mountain View, CA
    2 days ago
  • $190.61k - $269.1k

     ...accelerators. If you are an engineer with strong technical and...  ...You will develop logic design, register transfer level (RTL) coding, and simulation for...  ...equivalence checks Drive silicon bring-up and post-silicon...  ...design and implementation for ASIC/SoC development Preferred... 
    Senior
    Local area
    Immediate start
    Shift work

    Intel

    Santa Clara, CA
    1 day ago
  • ScOp Venture Capital is looking for a Senior Design and Verification Engineer to work on cutting-edge AI systems for EDA. You will collaborate closely with...  .... The ideal candidate has a strong background in RTL design, functional verification, and experience with simulation... 
    Senior

    ScOp Venture Capital

    Santa Clara, CA
    1 day ago

Do you want to receive more vacancies?

Subscribe and receive similar vacancies to Senior ASIC/VLSI Design Engineer - RTL, DFT & Bring-up. Be the first to apply!