Lead Digital IP Verification Engineer (SystemVerilog/UVM)
NXP Semiconductors
NXP Semiconductors is looking for a Digital IP Principal Verification Engineer based in Austin, Texas. This role requires designing and implementing verification strategies for IP or sub-system levels. Candidates should have a minimum of 6 years of experience in verification with strong skills in Verilog and SystemVerilog. Responsibilities include writing verification plans, debugging test cases, and leveraging AI to enhance productivity. A BSEE/BSCE/BSCS degree is required, and an MSEE/MSCE/MSCS is a plus. Join NXP and contribute to innovative technologies in a dynamic environment. #J-18808-Ljbffr NXP Semiconductors
- ...ai, Inc. is looking for a Design Verification Engineer to join our Internal IP DV team in Austin, Texas. In this... ...performance of custom IPs by developing UVM/SystemVerilog testbenches and executing... ...have a strong background in UVM, digital design, and debugging skills. Benefits...DigitalWork at office
- ...Semiconductors, located in Austin, Texas, is seeking a Senior Verification Engineer to join their MME MCU/MPU Digital IP team. This role involves defining verification... ...degrees, showcasing proficiency in Verilog and SystemVerilog. Collaboration with global teams to drive best...Digital
$150k - $165k
Encore Semi Llc is seeking a Senior Design Verification Engineer to verify complex digital systems, including ARM-based CPUs. The role includes developing UVM/SystemVerilog testbenches and automating testing processes. The ideal candidate should have 10+ years of ASIC verification...DigitalRemote job- ...is seeking a highly motivated Hardware Verification Engineer in Austin, Texas. In this role, you will verify complex digital designs, especially focusing on DSP and... ...responsibilities include developing test benches using SystemVerilog and UVM, designing verification plans, and...Digital
- ...technology company in aerospace is seeking a Senior Verification Engineer I in Austin, Texas. The ideal candidate... ...at least 4 years of experience in FPGA digital design verification, proficient in VHDL, Verilog, and SystemVerilog. This position involves developing...DigitalFull time
- A leading semiconductor company in Texas is seeking a Design Verification Engineer to join its team. This role involves planning and executing... ...the verification of complex digital designs using advanced... ...tools like System Verilog and UVM. The ideal candidate will have...Digital
- ## Principal Digital IP Verification EngineerApplylocations: Austin (Oakhill,... ...scoreboards, and leverage advanced UVM VIPs* Develop directed and... ...* Develop and maintain SystemVerilog assertions (SVA)* Apply... ...Mentor and grow a small team of engineers**Cross-Functional...DigitalWork at officeLocal area
- ## Digital IP Principal Verification EngineerApplylocations: Austin (Oakhill, Office)time... ...IP Principal Verification Engineer**Primary Location:**... ...stimulus in System Verilog (UVM), random test scenarios, algorithmic... ...verification.* Verilog, SystemVerilog, UVM coding skills...DigitalWork at officeLocal area
- A leading technology company in Austin is looking for a Design Verification Engineer to enhance custom IPs for cutting-edge technologies. This position... ...requires expertise in UVM and SystemVerilog, strong debugging... ...experience in verifying digital designs and will enjoy...DigitalWork at office
$2,000 per month
...investors and staffed by leading engineers, Etched is redefining... ...are seeking a Design Verification Engineer to join our Internal IP DV team. You will... ...Develop and maintain UVM/SystemVerilog testbenches for high-performance... ...skills for complex digital designs. Solid...DigitalWork at officeRelocation packageShift workNight shift- Silicon Labs seeks a Digital Verification Engineer I in Austin, Texas, to verify ASIC IP blocks for IoT modem designs. This role requires a degree in Electrical Engineering and proficiency in Verilog/SystemVerilog. You'll develop verification environments, analyze results...DigitalFlexible hours
- A leading technology company in Austin is seeking an experienced ASIC Verification Engineer to work on system-level IP projects. Candidates should have a strong background in verification methodologies... ...with expertise in System Verilog and UVM. This position offers a competitive...
- ...Semiconductors in Austin, TX is looking for a Principal Digital IP Verification Engineer to lead the verification of advanced microcontroller digital... ...analytical mindset, extensive experience in Verilog/SystemVerilog, and hold a BSEE or higher with relevant work...DigitalWork experience placement
- A tech start-up is seeking a Verification Team-Leader to oversee a team of engineers working on complex digital verification projects. The ideal candidate will have... ...communication protocols and verification tools like SystemVerilog and UVM will excel in this role. #J-18808-Ljbffr...Digital
- ## IP Verification EngineerAustin,Texas,United StatesFind out... ...Design Verification Engineer — ASIC IP** **Silicon... ...technical and organizational lead — this is where you... ...and building UVM environments from a clean... ...and/or top level Strong SystemVerilog/UVM chops — not just using...Temporary workLive inLocal area
$120k - $225k
...hiring experienced Design Verification Engineers from junior to senior... ...of traditional digital systems at the same power... ..., custom analog IP, compiler, emulation... ...and execution using UVM or other advanced DV... ...Understanding of Verilog, SystemVerilog, and UVM. ~ Proven...Digital- ...Austin, Texas is seeking a Senior Design Verification Engineer specializing in ASIC IP development. In this position, you will lead verification efforts on cutting-edge 5G... ...strong background in RTL verification, SystemVerilog, and UVM, with additional knowledge in embedded...
- Etched.ai, Inc. in Austin is looking for a Design Verification Engineer to join their Interface IP DV team. The successful candidate will ensure architecture... ..., and develop verification environments using UVM/SystemVerilog. With a fast-paced startup culture, Etched values...
- Senior Design Verification Engineer — ASIC IP Silicon Verification | 5G Infrastructure... .... Join our team to lead the verification of critical... ...- designing and building UVM environments from a clean... ...and/or top level. Strong SystemVerilog/UVM skills - not only use...
- ...technology company in Austin is seeking a Design Verification Engineer to join their Interface IP DV team. The role involves collaborating with architects... ...verification experience, alongside expertise in UVM/SystemVerilog and industry-standard IP interfaces. This position...Relocation package
- NXP Semiconductors is looking for a Senior Design Verification Engineer in Austin, TX to define and write verification plans based on requirements for digital IP components. You will be responsible for creating stimulus in System Verilog, debugging testcases, and collaborating...Digital
- ...motivated Mixed-Signal Verification Engineer III to support verification... ...analog and mixed-signal IP integrated within digital-on-top SoC environments.... ...contributor role will lead development and execution... ...strong expertise in SystemVerilog, UVM methodologies, and behavioral...Digital
- ## Senior Verification EngineerApplylocations: Austin (... ...within the MME MCU/MPU Digital IP team. We develop best... ...leverage advanced UVM VIPs* Develop directed... ...Develop and maintain SystemVerilog assertions (SVA)* Apply... ...grow a small team of engineers**Cross-Functional...DigitalWork at officeLocal area
$220.92k - $311.89k
...a Senior Formal Verification Engineer, you will play a... ...correctness of complex digital designs using... ...for complex SoC IP blocks and subsystems... ...using SystemVerilog Assertions (SVA)... ...Document test plans and lead technical reviews... ...Familiarity with UVM‑based simulation...DigitalLocal areaShift work$84k - $156k
...NASDAQ: SLAB) is the leading innovator in low-... ...join the Modem Verification (IP Verification)... ...verifying complex digital designs for modem... ...using Verilog and SystemVerilog. Support automated... ...cross‑functional engineering teams.... ...plus: Knowledge of UVM (Universal Verification...DigitalInternshipFlexible hours- ...-tier investors and staffed by leading engineers, Etched is redefining the infrastructure... ...We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with... ...IP team Develop and maintain UVM/SystemVerilog-based verification environments...Work at officeShift work
$150.5k - $279.5k
Staff Digital Verification Engineer - Austin, TX Responsibilities Block and IP Verification - create and execute metric‑driven verification... ...- architect and implement UVM‑based verification components... ...Strong knowledge of Verilog, SystemVerilog, UVM, and C/C++. Experience...DigitalFlexible hours$143.15k - $265.85k
...NASDAQ: SLAB) is the leading innovator in low-power... ...involves executing a verification plan on digital IP blocks using a... ...candidate should have built UVM test benches from... ...Electrical/Computer Engineering* Strong knowledge of Verilog, SystemVerilog, UVM, and C/C++* Knowledge...DigitalFlexible hours- ## Senior Design Verification EngineerApplylocations: Austin... ...*Design Verification Engineer****Business Line... ...Advanced Chip Engineering's Digital IP team defines and... ...in System Verilog (UVM), random test scenarios... ....* Verilog, SystemVerilog, UVM coding skills required...DigitalWork at officeLocal area
- ...Apple’s Silicon Engineering Group has embarked... ...to take the lead and contribute to... ...multiple sophisticated IP-level DV... ...highly reusable UVM TB, implement effective... ...DV methodology, verification on accelerated... ..., C++, Java, or SystemVerilog). Coursework in Digital Design....DigitalFlexible hours
Do you want to receive more vacancies?
Subscribe and receive similar vacancies to Lead Digital IP Verification Engineer (SystemVerilog/UVM). Be the first to apply!
- lead engineer Austin, TX
- lead industrial engineer Austin, TX
- lead system engineer Austin, TX
- lead network engineer Austin, TX
- lead product engineer Austin, TX
- lead web developer Austin, TX
- lead infrastructure engineer Austin, TX
- lead operating engineer Austin, TX
- senior verification engineer Austin, TX
- verification & validation engineer Austin, TX

