Quantum TSV Integration Engineer

Job Summary GlobalFoundries Fab8 is seeking a highly skilled and motivated R&D TSV engineer to become part of the Quantum Advanced Packaging team. The primary responsibility is to own development and integration of cryogenic, superconducting TSV technologies enabling high-density vertical interconnects for scalable quantum packaging from concept through manufacturing. Essential Responsibilities Lead development of through-silicon via (TSV) processes for cryogenic and superconducting applications. Define TSV architectures, including: Superconducting liners (e.g., Nb, Al‑based) Dielectric isolation schemes Via geometries (diameter, depth, pitch) Ensure TSV designs are optimized for: Low-loss electrical/RF signal transport Cryogenic thermal and mechanical stability Own end‑to‑end TSV integration flows across: Via etch, liner deposition, dielectric, and metallization Wafer thinning, reveal, and backside processing Integration into 2.5D/3D packaging stacks Drive process integration planning to enable prototyping and qualification across programs. Develop TSV solutions for superconducting interposers and 3D integration platforms. Support integration with: Bump/interconnect layers Redistribution routing layers (RDL) Assembly and bonding flows Ensure TSVs enable high-density vertical interconnects for quantum system scaling. Enable prototype builds and development lots, ensuring smooth execution through fab and assembly flows. Support transition from R&D to pilot to manufacturable flows. Collaborate with device/test teams to ensure TSVs meet cryogenic electrical performance requirements (DC + RF/microwave) and low resistance/minimal loss for superconducting operation. Support characterization of signal integrity (noise, cross‑talk), thermal leakage across vias, and develop strategies to improve TSV yield and process robustness. Support integration reliability under cryogenic conditions. Identify and analyze failure modes such as: Liner defects / discontinuities Delamination or cracking during thermal cycling Void formation or via integrity issues Lead root‑cause analysis and corrective actions. Work closely with materials teams to select TSV liner and dielectric materials compatible with superconducting operation, understand cryogenic behavior, and optimize interface integrity. Define requirements for TSV-specific process tools (Deep silicon etch, conformal deposition, wafer thinning, and reveal) and collaborate with equipment vendors and suppliers to develop new capabilities. Support qualification of new tooling and materials. Interface across interconnect, assembly, integration, device and system engineering teams to ensure co‑optimization of TSVs with the full packaging stack. Drive development of next‑generation TSV scaling, including smaller diameters and higher aspect ratios, and contribute to the cryogenic 3DHI roadmap and APPC capability build‑out. Evaluate novel via concepts (e.g., superconducting‑lined, partially filled, or air‑gap vias). Generate TSV integration flows and specifications, design rules and process documentation, provide technical updates, reports, and data‑driven insights. Contribute to IP, publications, and conference outputs. Other Responsibilities Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs. Take part in hiring of other Advanced Packaging team members. Mentor and guide new hires. Other duties as assigned by manager. Required Qualifications Education: Master's in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science or a related field from an accredited degree program. MS degree with at least 8 years of prior related work experience. Must have at least an overall 3.0 GPA and proven good academic standing. Language: Fluency in English (written & verbal). Travel: Up to 20%. Proficient in designing TSV processes and integration for cryogenic and superconducting applications. Strong written, verbal, planning and organizational skills. Experience in root‑cause analysis and corrective action in semiconductor processing. Preferred Qualifications PhD education level preferred with at least 5 years of related work experience. Demonstrated prior leadership experience in the workplace, school projects, competitions, etc. Project management skills for innovating and executing solutions that matter. Experience navigating ambiguity in research and development. Strong communication and organizational skills. Salary Expected Salary Range: $98,000.00 - $176,000.00. The exact salary will be determined based on qualifications, experience and location. Additional Information GlobalFoundries is an equal‑opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation while our employees feel truly respected, valued, and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation, and medical and/or physical abilities. All offers of employment are conditioned upon successful completion of background checks, medical screenings as applicable, and subject to the respective local laws and regulations. If you need a reasonable accommodation for any part of the employment process, please contact us by e‑mail at View email address on click.appcast.io and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case‑by‑case basis. Don't hesitate to apply. We shape what is essential at GlobalFoundries. Our diverse and global team shares a culture of respect and inclusivity. #J-18808-Ljbffr GLOBALFOUNDRIES US Inc.