Verification Engineer
Ubitium GmbH
Focus areas include but are not limited to: RTL and system-level verification, UVM, assertions, coverage, debug. Prospective team members require strong Verilog/SystemVerilog and UVM; RTL debug skills; processor/SoC experience; RISC-V experience preferred. Master’s degree (or equivalent) and 2+ years of hands-on experience in a relevant role. Relocation required. Currently 4 days on-site, 1 day remote. Policy may change. #J-18808-Ljbffr Ubitium GmbH
Vacancy posted 2 days ago
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