Design Verification Engineer - Interface IP
Akaasa Technologies
Design Verification Engineer Interface IP
Location: San Jose, CA Hybrid
Duration: 12 Month Contract To Hire
About the Role
Our Interface IP Design Verification team is looking for a Design Verification Engineer to help ensure our IP subsystems and interfaces meet architectural requirements from first principles through sign-off. You'll partner closely with architects, designers, and external vendors to validate correctness and performance across the entire hardware-software stack. Success in this role calls for strong technical depth, creative problem-solving, and comfort navigating complex, ambiguous verification challenges.
What You'll Do
Take end-to-end ownership of verification for one or more IP subsystems - PCIe, Ethernet, CPU (ARC/ARM), low-power peripherals, or sensors
Work directly with internal IP teams to understand and align on vendor IP configurations
Build and maintain UVM/SystemVerilog verification environments that confirm functional correctness, performance, and spec compliance
Partner with integration and SoC DV teams to ensure external IPs interact cleanly within the larger chip architecture
Own coverage closure from end to end - defining metrics, identifying gaps, and driving thorough verification across corner cases and stress conditions
Vacancy posted 3 days ago
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