Design Verification Engineer

Design Verification Engineer

We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.

Key Responsibilities:

• Develop and maintain UVM-based verification environments
• Create test plans, testcases, and coverage models
• Perform functional verification of RTL designs
• Debug RTL and testbench issues
• Drive coverage closure (functional + code)

Required Skills:

• Strong hands-on with SystemVerilog and UVM
• Experience in block-level verification
• Good understanding of digital design fundamentals
• Experience with debug tools (Verdi, DVE, etc.)

Good to Have:

Exposure to low-power verification (UPF)