Senior RTL Design Engineer - CPU Frontend

Responsibilities

• Architect, design, and implement new features, performance improvements, and ISA extensions in RISC‑V CPU core generators using Chisel.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements of that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
• Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
• Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
• Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
• Microarchitecture development and specification.
• Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.

Requirements

• BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
• 3+ years of design experience.
• Academic or professional experience with CPU RTL design in one or more of the following areas: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, TLBs.
• Proficiency in hardware (RTL) design in Verilog, SystemVerilog, or VHDL.
• Strong software engineering skills/background, including: object‑oriented, aspect‑oriented, and particularly functional programming; templated metaprogramming; compiler infrastructures, particularly for domain‑specific languages; data modeling, particularly intermediate representations for optimizing or transforming compiler passes; test‑driven development, particularly ability to write adaptive unit tests.
• Attention to detail and a focus on high‑quality design.
• Ability to work well with others and share the belief that engineering is teamwork.

Nice‑to‑Haves

• Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software.
• Knowledge of RISC‑V architecture.
• Expertise in CPU processor designs in one or more of the following areas is a plus: instruction fetch; instruction decode; register renaming and instruction scheduling; vector units; load‑store unit.
• Knowledge of verification principles, testbenches, UVM, and coverage.
• Experience with Git/GitHub, Jira, Confluence.

Pay & Benefits

Consistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. Base Pay Range: $158,760.00 – $194,040.00. In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity. The role also offers a comprehensive benefits package including healthcare, retirement plans, paid time off, and more.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.